Issue



III-V MOSFETs for future CMOS transistor applications


12/01/2008







M. Passlack, U. of California, San Diego, San Diego, CA USA;
R. Droopad, Texas State U., San Marcos, TX USA;
I. Thayne, A. Asenov, U. of Glasgow, Glasgow, UK

III-V semiconductors are commonplace in laser and lighting applications and provide enabling components, such as power amplifiers, for mobile products including handsets and WLAN transceivers. In recent years, research into III-V semiconductors to complement silicon in mainstream electronic applications, such as microprocessors, has dramatically accelerated. Some interesting concepts have emerged that show promise to further enhance CMOS performance and provide new levels of functionality.

CMOS has enjoyed decades of prosperity with reliance on core materials, such as silicon for the transistor body, and silicon dioxide for the gate dielectric. Yet focus has shifted during the last decade with the introduction of new materials, such as silicon germanium for the ohmic contact region of p-channel transistors, and hafnium-based gate dielectrics to improve device performance and energy efficiency. Truly revolutionary changes may still lie ahead with the envisioned replacement of the very essence of CMOS: the silicon channel. Besides alternative channel materials, such as germanium and rather exotic options like graphene, future CMOS generations may finally draw momentum from a rather unlikely contender: III-V semiconductors, which have been used in commercial applications, such as communications and optoelectronics, for years.


Figure 1. Cross-sectional schematic view of a) a PHEMT and b) a III-V quantum well MOSFET with virtual drain/source extensions.
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Research efforts by Intel and others have resulted in n-channel pseudomorphic high-electron mobility transistors (PHEMT) using III-V quantum wells. These efforts have resulted in impressive improvements over silicon channels, both in terms of energy efficiency and speed, with enhanced electron channel mobility as the key performance boosting parameter [1,2]. Although such transistors are perfect test vehicles to demonstrate performance enhancement, their nonplanar design and Schottky gate electrode, as shown in Fig. 1a, may render them unsuitable for CMOS. For a PHEMT, in contrast to a MOSFET, the channel layer is separated from the metal gate electrode by a barrier material that provides only a relatively small conduction-band-edge discontinuity, resulting in large parasitic leakage currents and limited transistor scalability.

The III-V MOSFET challenge

With the development of n-MOSFETs with III-V quantum well channel layers at Freescale Semiconductor and Motorola during the last twelve years [3], a technology platform has been established that is expected to facilitate the penetration of III-V channels into CMOS. Some noticeable features are the planar layout, a shallow channel defined by the semiconductor heterostructure, and the use of virtual drain/source extensions replacing conventional ion implanted extensions as illustrated in Fig. 1b. MOSFETs displaying many of the features shown in Fig. 1b were first implemented on a GaAs substrate with a 10nm high-k GdGaO/Ga2O3 gate dielectric (k =19.5) and an InGaAs channel layer with an indium mole fraction of 30%.


Figure 2. Measured terminal characteristics (lines) of a typical 1µm GaAs n-channel MOSFET including a) ID-VD and b) ID-VG. The transistors are enhancement-mode (defined as threshold voltage Vt > 0V for an n-channel FET) with a Vt of 0.26V. Peak transconductance, on-resistance, and maximum gate current are 477µS/µm, 1900µm, and 20pA, respectively. The symbols are numerical data obtained from a Synopsis simulator using hydrodynamic drive with electron transport calibrated against production PHEMT (courtesy of O. Hartin, Freescale Semiconductor).
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In a collaborative effort between Freescale Semiconductor and the University of Glasgow, n-channel enhancement-mode GaAs-based MOSFETs that perform in line with ideal model predictions were fabricated in late 2006 [4], after more than 40 years of research in the field. Both measured ID-VD and ID-VG characteristics (lines) of a typical 1µm MOSFET with a peak channel mobility of 5,500cm2/Vs are shown in Fig. 2, along with numerical simulation data (squares). The peak channel mobility exceeds that of silicon high-k n-channel MOSFETs by more than a factor of 20. Transistor performance using transconductance (dID/dVG) as the key metric is benchmarked against all other published data of planar enhancement-mode GaAs MOSFETs since the first report appeared in 1965 (Fig. 3). Among other factors, the success of this technology has been enabled by the discovery of a device-quality interface that arises from the atomic bonding configuration between deposited Ga2O3 and GaAs, a unique interface system on GaAs [5].


Figure 3. Benchmarking of planar GaAs enhancement-mode MOSFETs from the first report in 1965 to present day showing peak extrinsic transconductance over gate length. Our MOSFET data improve on prior art by a factor of 50-5000 and most recent data match ideal model predictions. MOSFETs using a silicon interlayer are not shown because the channel forms in both GaAs and silicon.
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Originally, Freescale developed GaAs-based MOSFET technology utilizing an In0.3Ga0.7As quantum well channel layer for radio frequency (RF) power application requiring high efficiency at low voltage, such as power amplification and RF switching in front-ends of mobile products. A technology presently dominating this platform comprises a monolithic integration of a GaAs PHEMT with a heterojunction bipolar transistor (BiHEMT), where each device performs specific functions and uses its own epitaxial layer structure. A GaAs-based MOSFET technology would not only provide improved performance on the PHEMT side, but may also enable higher levels of integration and new functionality while simplifying the fabrication with all functionality implemented using one type of device. A first benchmarking study against WIN Semiconductor’s BiHEMT process [6] is shown in Fig. 4.


Figure 4. Benchmarking of 1µm GaAs MOSFET technology against WIN Semiconductor’s 0.5µm HW2 enhancement-mode GaAs PHEMT production technology. The MOSFET threshold voltage can be easily shifted by selecting a gate metal of appropriate workfunction to accommodate different functionality, such as enhancement/depletion logic and power amplification without need of a drain switch.
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III-V n-MOSFETs for CMOS

Future III-V transistors for CMOS are likely to use InGaAs channel materials with indium mole fractions >70%, or materials of even higher electron mobility, such as InAs and InSb for maximum performance improvements over silicon. There are indications that atomic bonding configurations at indium-containing surfaces differ from that of GaAs. III-V CMOS transistors will likely not be able to draw directly from the successful Ga2O3-GaAs interface, and molecular beam epitaxy -- the technique used to manufacture GaAs MOSFETs -- will have difficulty meeting the volume and wafer size requirements of CMOS. Nevertheless, III-V CMOS transistors will likely share common attributes with our quantum well GaAs MOSFETs such as device physics, general methods and techniques of manufacturing, design methodology for devices and test structures, and the ability to benefit from the natural properties of indium-containing semiconductors. In fact, we believe that learning from the success of GaAs MOSFETs may substantially accelerate development of III-V transistors for CMOS.


Figure 5. a) Cross-sectional TEM image of a thin body MOSFET layer structure with In0.75Ga0.25As channel grown on InP substrate and b) ID-VD terminal characteristics of a corresponding 1µm MOSFET with 5nm GdScO3 gate dielectric. The equivalent oxide thickness in b) including the 2nm InAlAs layer is 1.7nm. The device width is 100µm and VD is corrected for probe resistance. The average electron velocity within the 1µm long channel is 1.8x107cm/s.
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Recently, we have also demonstrated the first planar quantum well III-V MOSFET featuring a 5nm gadolinium scandate gate dielectric, and an In0.75Ga0.25As channel with an electron mobility >7700cm2/Vs in a thin body architecture suitable for CMOS as shown in Fig. 5 [7]. With the source-drain separation of 3µm likely being larger by a factor of 100, compared to the requirements of CMOS at the 22nm node and beyond, the measured on-resistance of 555-µm looks rather promising when compared to CMOS requirements of ˜150-µm [8]. This low on-resistance is accomplished through the use of shallow (12nm) virtual source/drain extensions that replace standard ion implantation. We have already demonstrated virtual channels in MOSFET test structures with 4µm contact separation having electron sheet carrier concentrations >5x1012cm-2 and mobilities of ˜8,500cm2/Vs, resulting in sheet resistivity of <150/sq. for extensions as shallow as 16nm, and carrying current densities up to 1.5mA/µm.


Figure 6. Performance metrics of high indium mole fraction InGaAs channel MOSFETs (red data points) including a) peak transconductance over subthreshold swing S, the label of each data point includes the gate length and the interface state density below the conduction band minimum inferred from S; and b) on-resistance over extension depth of planar III-V MOSFETs. GaAs MOSFET data are shown for comparison purposes (blue diamonds).
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Finally, benchmarking of present contenders for III-V n-channel CMOS will shed some light on the state of the technology and remaining challenges. Peak transconductance as a measure of on-state performance is plotted against sub-threshold swing as major off-state metrics for CMOS contenders with GaAs MOSFETs displayed for comparison purposes in Fig. 6a. Sub-threshold swing S should be close to the theoretical limit of ˜60mV/dec that is demonstrated for GaAs MOSFETs. However, S is substantially elevated for all present III-V CMOS contenders, most likely because of the excessively high density of defect states at the oxide-semiconductor interface. In a further comparison, on-resistance is depicted as a function of extension depth in Fig. 6b for III-V CMOS contenders, again showing GaAs MOSFETs as a reference.

For implanted III-V MOSFETs, the extension depth is set to equal the implant projected range, and for virtual III-V extensions, the extension depth equals the depth of the channel layer. Obviously, shallow implanted extensions will have serious difficulty meeting CMOS requirements of <150-µm, while III-V MOSFETs with virtual shallow extension with high electron mobility appear to be promising candidates for scaled CMOS devices. A study of scaled III-V MOSFETs with virtual extensions using Monte-Carlo simulations can be found in [14].

Conclusion

The development of III-V thin body MOSFETs with shallow virtual extensions, the demonstration of significant performance improvement of III-V short channel PHEMTs over silicon n-channel MOSFETs, and other efforts in industry and academia have provided encouraging progress towards the utilization of III-V channel materials in future CMOS devices. Significant challenges however remain, including the development of a device quality oxide-semiconductor interface for channel materials with high indium mole fraction, the heterogeneous integration of III-V channels onto a silicon substrate with minimum buffer layer thickness, and others. Eventually, success in integrating III-V CMOS channels onto a silicon substrate may provide fertile grounds for combining diverse functionality such as digital, optoelectronic, and high performance RF devices onto a common silicon substrate.

References

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  2. D-H. Kim et al., “Logic Performance of 40nm InAs HEMTs,” International Electron Devices Meeting (IEDM) Tech. Digest, pp. 629-632, 2007.
  3. “Enhancement mode metal-oxide-semiconductor field effect transistor and method for forming the same,” US Patent 6,963,090, issued 11/08/05.
  4. R.J.W. Hill et al. “Enhancement-mode GaAs MOSFETs with In0.3Ga0.7As Channel, Mobility Over 5000 cm2/Vs and Transconductance Over 475µS/µm,” IEEE Electron. Dev. Lett., vol. 28, no. 12, pp. 1080-1082, 2007.
  5. M. Hale et al., “Scanning Tunneling Microscopy and Spectroscopy of Gallium Oxide Deposition and Oxidation on GaAs(001)-c(2x8)/(2x4),” J. Chem. Phys., vol. 119, no. 13, pp. 6719 - 6728, 2003.
  6. C. K. Lin et al., “Monolithic Integration of E/D-mode pHEMT and InGaP HBT Technology on 150-mm GaAs Wafers,” CS MANTECH Conference Proc., pp. 251-254, May 14-17, 2007, Austin, Texas, USA
  7. R.J.W. Hill et al., “1µm gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737µS/µm,” Electronics Letters, vol. 44, no. 7, pp. 498-500, 2008 and vol. 44, no. 21, 2008.
  8. http://www.itrs.net/
  9. S. Koveshnikov et al., “High Electron Mobility (2270cm2/Vs) In0.53Ga0.47As Inversion Channel n-MOSFET with ALD ZrO2 Gate Oxide Providing 1nm EOT,” 66th Device Research Conf. Digest, pp. 43-44, Santa Barbara, 2008.
  10. Y. Sun et al., “High Performance Long- and Short-Channel In0.7Ga0.3As Channel MOSFETs,” 66th Device Research Conf. Digest, pp.41-42, Santa Barbara, 2008.
  11. Y. Xuan et al., “High Performance Submicron Inversion-Type Enhancement-Mode InGaAs MOSFETs with ALD Al2O3, HfO2, and HfAlO as Gate Dielectrics,” IEDM Tech. Digest, pp. 637-640, 2007.
  12. Y. Xuan et al., High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1A/mm,” IEEE Electron. Dev. Lett., vol. 29, no. 4, pp. 294-296, 2008.
  13. T.D. Lin et al., “Self-Aligned Inversion-Channel and D-Mode InGaAs MOSFET Using Al2O3/Ga2O3(Gd2O3) as Gate Dielectric,” 66th Device Research Conf. Digest, pp. 39-40, Santa Barbara, 2008.
  14. K. Kalna et al., “Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs,” IEEE Trans. Electron Devices, vol. 55, no. 9, pp. 2297-2306, 2008.

Matthias Passlack received his MS and PhD in electrical engineering from the Technical U. of Dresden, Germany. He is now with the U. of California ??? San Diego, 9500 Gilman Drive, La Jolla, CA 92093 USA; ph.: 480-636-6982; e-mail [email protected].

Ravi Droopad received his BS in electronics and communication engineering from the U. of Birmingham, UK, and his PhD in semiconductor physics from the Imperial College of London, UK. He is now a professor at Texas State U. ??? San Marcos, TX, USA.

Iain Thayne received his BS and PhD in physics and electronic engineering from the U. of Glasgow, Glasgow, UK He is now a professor at the U. of Glasgow, Glasgow. UK.

Asen Asenov received his MS in solid state physics from Sofia U., Bulgaria, and his PhD in physics from the Bulgarian Academy of Science, Sofia, Bulgaria. He is now a professor at the U. of Glasgow, Glasgow, UK.