Raising the bar on wafer edge yield—an etch perspective
11/01/2008
By: V. Vahedi, M. Srinivasan, A. Bailey, Lam Research Corporation
A variety of plasma techniques have been introduced to manage the unique dielectric and conductor etch challenges encountered at the wafer’s edge, as well as address bevel-clean challenges that impact yield. This article discusses advances in etch and bevel-clean technologies that have been developed to improve yield at the wafer’s edge.
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Consumer demand for high functionality at low cost continues to drive chip makers to shrink geometries and increase yields. With tighter tolerances and larger wafers, it is both more important and more difficult to maintain uniformity in etch profiles and critical dimensions (CDs) out to the extreme edge of the wafer. The beveled edge of the wafer is a geometric discontinuity with different conditions compared to the rest of the wafer’s planar surface. As CD tolerances become tighter, the systemic differences encountered at the wafer’s edge are playing a larger role in the yield equation.
Edge die yield is also impacted by defects originating from the wafer’s edge. Excess deposited material can accumulate there, where it can flake and chip during subsequent operations. In immersion lithography, fluid forces generated by rapid stage movements can delaminate film edges, and the fluid provides a ready mechanism to transport debris from the wafer edge to the active area.
Finally, as wafer size has grown, so has the number of die residing near the edge. For example, the outer 20mm of a 300mm wafer can contain up to 25% of the wafer die. At the same time, shrinking the device size has decreased the CD tolerance. This includes tolerance for differences in process performance associated with edge effects, which makes cross-wafer CD uniformity increasingly important in maximizing process yield. As a result, tighter overall wafer CD uniformity requirements make maximizing yield at the wafer’s edge even more difficult.
Emerging etch challenges
The International Technology Roadmap for Semiconductors (ITRS) [1] currently mandates a production gate CD uniformity requirement of less than 2.0nm, 3-σ variation. That requirement will shrink to <1.0nm by 2010. In addition, emerging technologies are introducing new materials and processes such as high-k/metal gates, ultra low-k dual-damascene structures, and a growing number of multi-layer etches, all of which present additional challenges in terms of achieving CD uniformity requirements. A variety of plasma-etch techniques have been introduced to manage the unique dielectric and conductor etch challenges encountered at the wafer’s edge, as well as address bevel-clean challenges.
Dielectric etch solutions for improved uniformity
Adjustable gap control and gas tuning have both proven to be useful techniques for delivering improved etch uniformity across the wafer surface all the way out to the edge. The first is used to vary the distance between the plasma source and the wafer surface. The second controls how and where the gas is injected.
A number of processes, such as critical mask opens and trench etches, require that the plasma be optimized for the particular film being etched. Adjusting the gap controls plasma uniformity, enabling this level of process optimization. Dynamic step-by-step gap tuning makes possible the in situ multi-film stack etches required for emerging applications, such as combined-mask-open and high-aspect-ratio etch.
Dielectric etch processes are typically ion-limited, and the etch rate depends on the ion flux. Adjusting the electrode gap changes plasma uniformity, which changes the radial etch rate uniformity to allow for radial tuning. For those etch processes with neutral-limited regimes, such as a low-pressure photoresist strip, the etch rate depends on etchant flux. In such processes, the gap size also affects center-to-edge CD uniformity. With a smaller gap, the etchant is depleted unevenly over the wafer with less depletion toward the edge due to diffusion. With a larger gap, however, there is better radial diffusion of the etchant across the entire surface of the wafer, resulting in better cross-wafer uniformity.
Available data suggest that varying the gap to meet specific material and process requirements can deliver up to 20% better CD uniformity than that currently mandated by the ITRS. This technique provides distinct benefits in advanced applications, such as etching high-aspect ratio and ultra low-k dual damascene structures. For example, varying the gap when etching the hardmask and during the main etch can improve trench uniformity. Failure to achieve the required depth uniformity can result in worse sheet-resistance uniformity and degraded device performance.
In dual-damascene processes, adjustable gap control makes it possible to etch all the films in the stack in situ (sequentially in the same chamber), rather than in multiple chambers across multiple systems (Fig. 1). This optimizes CD uniformity while also helping to reduce process costs and speed manufacturing cycle times.
Uniformity can also be improved by controlling the way the plasma gas is injected between the center and edge of the wafer. Lam Research, for example, has an approach for delivering reactant gas via multiple zones at the center and nearer to the wafer’s edge. Adding multiple injection points can tighten the uniformity range across the wafer by up to 4%. Tuning gases can also be added near the edge of the wafer for additional center???edge composition control to further tune CD uniformity. These center-to-edge gas control techniques, combined with the ability to adjust the gap between the source and the wafer, allow for precise control for etch rate and CD uniformity at the wafer’s edge (Fig. 2).
Conductor etch solutions
Conductor etch systems have been the workhorse of the industry in defining the critical transistor dimensions for all device types. It is no surprise, therefore, that measures have been taken at every technology node to provide additional CD uniformity control across the wafer. Since the edge is a geometrical discontinuity, multiple features have been added over many chamber generations to focus specifically on the last 20mm of the wafer. Tunable gas injection and plasma uniformity enhancement across the wafer have become standard features. While all of these features have been necessary to globally tune uniformity by affecting ion and radical concentration imbalances, their sensitivity is diluted by the diffusive properties of these variables in a large chamber reactor. While the adjustable gap is an effective CD tuning knob in a narrow gap dielectric reactor, a similar feature in a wide-gap reactor would mainly affect etch-rate uniformity. Industry experience has demonstrated that, in conductor-etch processes, wafer temperature has a locally specific impact on etch rate and CD uniformity and is the most sensitive tuning control knob.
Innovations in spatial temperature control are key to shaping the etch profile in critical applications to meet ITRS CD uniformity requirements. Figure 3 (column A) is an example of baseline CD performance with no temperature compensation. In this case, the CD variation at the edge is relatively small compared to the overall CD variation across the wafer. Using current tuning capability, including advanced temperature control hardware, substantial improvements in overall CD variation are made (Fig. 3, column B). Here, the edge contribution to CD variation is comparable to that of the rest of the wafer. However, to meet CD control requirements for future technology nodes, variation from the wafer’s edge must be further addressed. Column C of Fig. 3 illustrates the implementation of edge-specific spatial CD tuning that minimizes the total variation, primarily by reducing the contribution of the edge relative to the rest of the wafer. Therefore, spatial fine-tuning could be used on other non-uniformities that occur elsewhere on the wafer.
Double patterning is an application where this technology plays a key role. In this application, overall CD control is critical in meeting not only the node-specific CD requirements, but also in keeping within overlay budget requirements. To optimize CD uniformity and keep within the overlay budget, spatial control of center-to-edge CDs between the first and second layers of the double-patterning process may be necessary.
Bevel-clean challenges and solutions
A recently published benchmark study [2], sampling 10 leading-edge fabs, shows a drop off in yield as high as 50% at the wafer’s edge. This yield loss has a number of causes, including bevel defect sources, a lack of thermal uniformity, new materials, shrinking CDs, and process technologies such as immersion lithography, film deposition, and chemical mechanical planarization (CMP).
Currently, typical edge-of-wafer particle defect sources include silicon oxide, silicon nitride, and polymer-based films. New materials used in advanced processes, such as porous low-k or organic films, however, tend not to adhere as well as these more traditional films. As a result, this kind of defect issue will likely grow worse with increasing use of new materials at smaller design nodes. Defects related to immersion lithography occur when material that failed to adhere to the previous layer is picked up and redistributed by the immersion fluid. Defects associated with immersion lithography can include particles, watermarks, and bridging. The amorphous carbon hardmasks used in some advanced processes are another source of edge-related defectivity. These are tensile films that tend to adhere poorly at the wafer’s edge and peel off in long streaks that ball up, creating large particle defects.
Traditionally, the primary bevel-cleaning methods have been either a wet chemical clean or CMP. Both these techniques can be effective for materials that react to the chemistries used. The effectiveness of wet clean techniques depends on managing the chemical contact area. As a result, this approach is limited in terms of controllability, although there are certain applications where a wet approach is preferred, for example when simultaneous backside cleaning is needed. CMP technology also has limited utility for bevel clean applications. While it offers superior wafer-to-wafer repeatability compared to wet cleans, the processing area is limited, and the clean is often incomplete at the wafer notch. CMP-based bevel cleans are also inappropriate for opened structures due to the significant risk of particle contamination within the structure, limiting customer integration schemes.
 Figure 4. Implementing a plasma bevel-clean process results in reduced electrical failures in the active device area. Data shown are for an STI module. |
Plasma-based bevel-clean technology is an approach that uses a capacitively coupled plasma chamber and cleans in the same manner that plasma-etch technology removes material from the die pattern. This approach uses a confined plasma to mitigate active area attack risks and ensure that the region cleaned is outside the device area. Figure 4 shows a reduction in electrical failures in an STI module resulting from the implementation of a plasma bevel clean.
Using a plasma-clean approach, common defect sources (common dielectrics, tungsten, polysilicon, and polymer-based films) are removed using selective plasma chemistries, and the target contact area can be limited to as little as 1mm from the wafer’s edge with excellent repeatability. This technology can easily fit into the process flow of most device integration schemes. Plasma technology can be used for front-end-of-line (FEOL) post-shallow trench isolation and post-gate or bitline cleans, back-end-of-line (BEOL) post-damascene dielectric cleans, and pre-immersion lithography to ensure a clean wafer edge and bevel. Productivity can also be improved by cleaning multiple layers sequentially in the same bevel clean chamber. Plasma-clean systems are currently used in production at multiple companies to perform bevel cleans on multiple film stacks, and overall yield improvements of up to 5% are being realized.
Conclusion
Two critical components for increasing yields at the wafer’s edge are superior etch technology and effective wafer bevel cleaning. The optimal etch technology should include capabilities such as adjustable gap control, gas tuning, and variable wafer temperature control to enable greater CD uniformity at the edge and across the wafer. In addition, maintaining a clean wafer bevel has been shown to be a critical factor in enhancing yield. A recent entry to bevel cleans, plasma technology provides greater application flexibility than traditional bevel clean approaches.
References
- International Technology Roadmap for Semiconductors; http://member.itrs.net.
- F. Burkeen, et al, “Visualizing the Wafer’s Edge,” KLA-Tencor YMS Magazine, Winter 2007.
Vahid Vahedi received his PhD in electrical engineering and computer science with emphasis on plasma physics from the U. of California at Berkeley. He is the vice president of Conductor Etch at Lam Research Corporation, 4650 Cushing Parkway, Fremont, CA 94538 USA; ph 510/572-8535; e-mail [email protected].
Mukund Srinivasan received his PhD in mechanical engineering from the U. of California at Berkeley. He is the vice president of Dielectric Etch at Lam Research Corporation.
Andrew D. Bailey III received his PhD in applied physics from the California Institute of Technology. He is a product line general manager in the Clean Products Group at Lam Research Corporation.