Seeking process windows for 32nm USJs using MSA
09/01/2008
Susan Felch, principal member of the technical staff, frontend development at Spansion, summarized research she conducted while at Applied Materials???and done with IMEC???at the West Coast Junction Technology Group meeting, sponsored by the northern California chapter of the American Vacuum Society (AVS) and held in conjunction with this year’s SEMICON West.
Going from 90nm to 65nm to 45nm, scaling USJs could be accomplished by controlling the diffusion using co-implants (e.g., fluorine and carbon) and by introducing strain to boost the “on” current, Felch explained to the meeting attendees. From 45nm to 32nm, however, more drastic changes had to be used, such as new materials (HK+MG) and lower threshold voltage (Vt) processes to control the amount of diffusion. “As we go from 32nm to 22nm to 16nm, we’ll have to start thinking about changing device architecture. The challenges are getting tougher and tougher,” said Felch. Therefore, precise implantation along with millisecond annealing (MSA) for diffusion-less annealing seems to be the answer for USJ scaling. (Figure 1 from John Borland’s presentation summarizes various MSA options.)
 Figure 1. Millisecond anneal as an option for 32nm for a) n-type and b) p-type devices. (Source: IMEC, J.O.B. Technologies) |
Reminding the attendees of just how challenging the road to scaled USJs will be, Felch pointed out that even the revised 2007 International Technology Roadmap for Semiconductors’ (ITRS) requirement for scaling of Lg and Xj for logic devices was changed from the previous unrealistic 70Å to 90 Å-100 Å, made possible because HK+MG lifted some of the burden. “This new requirement is still very, very tough,” she noted, adding that using a laser anneal-only approach appears to meet all the requirements for 32nm.
Felch presented data that illustrated the compatibility of MSA with HK+MGs, reviewing several options for HK+MGs: fully silicided/gate last (FUSI, a scheme IMEC has promoted), replacement gate (RPT, promoted by Intel), and metal-insert polysilicon (MIPS, a gate-first approach). For the MIPS approach, materials have to be able to withstand the thermal budgets of the anneal and be able to etch the new gate stack. Furthermore, when laser annealing is being used, the etching has to be perfectly straight with no footing. Data presented by C. Ortolland at this summer’s VLSI Technology conference shows that dopant implantation and placement are very sensitive to gate profile with diffusion-less anneal. “A good straight profile will give nice Vt roll-off characteristics,” said Felch.
 Figure 2. Diode leakage. (Source: IMEC/C. Ortolland) |
Another advantage of using laser annealing with the MIPS technique is that if a single metal is desired, it can be combined with a capping layer. Laser annealing thus enables the work function of the two metals can be adjusted. Showing data from IEDM 2007, Felch observed that when using capping layers (for either pMOS or nMOS), the threshold voltage of the gate stack can be adjusted by varying the laser power and annealing temperature. Additional data further illustrated ways to find implant and laser annealing conditions that give the same leakage obtained with spike anneal (which is the baseline reference), but with a trade-off in low leakage versus high activation, as the deep Ge-PAI degrades leakage by >1000?? (see Figs. 2 and 3).
 Figure 3. Defects positions. (Source: IMEC/C. Ortolland) |
MSA must also be compatible with strain boosters used in logic devices; therefore, laser annealing must be compatible as well, but Felch noted that increasing the annealing temperature also increases the number of defects in the SiGe, since its melting temperature (1200??C-1300??C for a 20%-40% Ge concentration) is much lower than that of Si (1410??C). It is therefore necessary, she said, to try to find process windows in the annealing space that will enable slightly higher temperatures to get better device activation and less leakage. Data on the effects of laser dwell times shows that at lower Ge concentrations, laser temperatures can be higher???however, using higher Ge concentrations will force the lowering of MSA temperatures. “If we go to shorter dwell times for the laser anneal, that will enable slightly higher MSA annealing temperatures,” Felch said.
She also presented data showing a small variation in microsheet resistance when using laser anneal due to the stitching of the laser beam. However, it was found that the impact of laser stitching in short channel devices is negligible compared to other sources of spread.
For 32nm USJs, Felch advocated the need for millisecond anneal (MSA)-only, but noted that various integration issues/compatibilities will need to be dealt with. The process will have to be compatible with the HK+MG stack if embedded SiGe is going to be used, which places limitations on how high the temperature can go to prevent the onset of defect formation. To get the required activation and defect annihilation (for low leakage), higher temperatures will be needed. In the mid-temperature range processes, it is important to minimize poly depletion and also get good mixing of the high-k dielectric and capping layer. “So for different customers’ integration schemes and device structure, we’re going to have to find a proper process window where we can get all of the benefits and compatibilities with MSA,” she said.
At 22nm and beyond, when traditional planar bulk CMOS devices run out of steam, Felch noted that the industry will probably have to go to some sort of multigate scheme such as FinFET. “We’ll get better control over gate-to-channel currents, lower off-state leakage current, better immunity to short channel effects, and higher mobility in these types of devices,” she said. But from a junction perspective, there are some very serious challenges, she added. For one, the thin fins tend to become fully amorphized; the question then becomes, how can they be regrown with good crystalline nature? ???D.V.