IMEC, ASML: Another step closer to production-worthy EUV
09/01/2008
Kicking off this year’s SEMICON West, IMEC said it has been able to achieve electrically functional 32nm SRAM cells (FinFETs). The fin and gate levels were prepared using immersion lithography, but the contact hole level was exposed using EUV lithography (hole size 50nm). The work was done on ASML’s alpha tool installed at IMEC.
Although this work has been done at 45nm and 32nm, the ultimate target is for a production-worthy EUV tool at 22nm. “Memory companies will most likely insert EUV at 22nm to obtain the required half-pitch, while many logic manufacturers will be able to delay EUV insertion until the 16nm node, which for them corresponds to a 22nm half-pitch,” explained Kurt Ronse, program director, advanced lithography, at IMEC, in an interview with SST.
 32nm SRAM device after EUV ADT exposures with various doses and after oxide etch. (Source: IMEC) |
The consortia also is studying which layers can be exposed using EUV beyond the contact layer, and which would be exposed using immersion lithography.
ASML’s roadmap still calls for a high-volume EUV tool to be ready by the end of 2009 or the beginning of 2010, according to Ron Kool, vice president of ASML’s EUV business unit. “We expect a source will be ready in time, and overlay numbers between EUV layers and immersion layers will be ready as well,” he said. The most important task now, he noted, is achieving high throughput???which translates to getting a source that supports that capability.
Stimulated by these milestones and with a concerted effort from all involved, IMEC is determined to advance EUV full speed towards the 22nm node. ???D.V.
IMEC/ASML 32nm EUV rivals Intel work
Essentially what IMEC and ASML have done is print 45nm CD contact holes with a 50% exposure latitude using EUV. With DUV, exposure latitude would have been 6??-8?? smaller and the most likely method would have been to print larger contacts and then shrink them with some resist-bloating method like RELACS. It’s likely that by “direct patterning” IMEC and ASML mean they don’t need such a step, or double patterning to hit the pitch needed. Oxide CDs are smaller than the resist CD, which suggests process control is key.
The SRAM design is not double-patterning friendly as Intel’s 32nm demo, but the accomplishment is real. This may be an example of using processing expertise to overcome design limitations, whereas Intel has done the opposite. That is the basic tension in DFM, and the payoff. ???M.D.L.