Model-based mask verification on 45nm logic gate masks
09/01/2008
In the continuous battle to improve critical dimension (CD) uniformity, especially for 45nm advanced logic products, one important recent advance is the ability to accurately verify the mask CD uniformity contribution to the overall global wafer CD error budget. By establishing a mask bias model (MBM), we are able to incorporate the mask CD uniformity signature into our modeling simulations and measure the effects on global wafer CD uniformity and hot spots. We also have examined several ways of proving the efficiency of this approach.
In most wafer process-simulation models, mask error contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by creating a short-range mask process model (MPM) for each unique mask process, and a long-range CD uniformity mask bias mask (MBM) for each mask. In this article we explore the MBM process.
 Figure 1. New mask model flow. |
By establishing an MBM, we are able to incorporate the mask CD uniformity signature into our modeling simulations, and measure the effects on global wafer CD uniformity and hot spots. We also have examined several ways of proving the efficiency of this approach, including the analysis of optical proximity correction (OPC) hot spot signatures with and without the MBM (Fig. 1), and by comparing the precision of the model contour prediction to wafer scanning electron microscope (SEM) images. We will show the different steps of MBM generation and use for advanced 45nm logic node layers, along with the current results of this new dynamic application to improve hot spot verification through Brion Technologies’ model-based mask verification loop.
OPC verification
Current OPC verifications do not accurately consider mask manufacturing errors as an input factor. The mask is assumed to be identical to the final fractured data when ordered at the mask shop. At the 45nm node and beyond, however, every nanometer counts in the global flow of transferring the desired design to the final wafer. For this reason, accurate modeling of the mask process is now critical to obtain necessary improvements.
In this study, we will decouple the effects related to the mask manufacturing process and take into account their impact in a new OPC modeling flow (Fig. 1). This modified flow allows us to perform model-based mask verifications. We will introduce a long-range CD uniformity mask bias map (MBM) into a new verification flow called mask bias mask verification. Finally, we will compare the different simulated hot spot results to actual wafer results and draw conclusions.
MBM: theory of operation
STMicroelectronics’ Crolles operation has developed a custom computer program (MELODIE 2) that is run during data tape-out, which automatically selects hundreds of points to be measured with a SEM at the mask shop for CD verification. This program attempts to create a wide distribution of sample points that are chosen with emphasis on critical wafer dimension placement.
 Figure 2. Fitted CD uniformity maps created with varying degrees of smoothing (). |
Brion has developed a capability that creates MBMs from numerous metrology or inspection tool sources [1,2]. For this study, our input data were the sparse CD SEM measurements that the MELODIE 2 software has already created for normal mask CD verification. Therefore, no additional work was needed during mask fabrication for MBM generation. Since the underlying CD variation is expected to be slow-varying across the mask, the MBM algorithm makes trade-offs between fidelity to each measurement and the smoothness of the overall fitted map. This “smoothing” function is user-controlled by a model parameter λ. Figure 2 shows the results of smoothing the same set of data with different λ settings. The individual black dots indicate individual SEM measurement points. The map color (or grayscale if reading in black and white) indicates the bias value assigned to that mask area. Note that higher λ values create a higher degree of smoothing. The user also has numerous options available, including rotation, X and/or Y mirroring, offset, and bias scaling.
MBMs used in OPC verification
MBMs are designed to be easily used during Lithography Manufacturing Check (LMC) Tachyon process window verification runs. In those runs, Tachyon compares the simulated results with dose, focus, and mask bias to the pre-RET design and reports problematic locations as defects, depending on the user-defined sensitivity threshold. Common defects include bridges, necks, CD errors, CD variations, line-end pullbacks and push outs, and missing and extra patterns.
In this section, we investigate the gate level of 45nm CMOS technology. The gate 45nm study used two models with a defocus condition of 100nm. The wafer was exposed on a 1.03NA, 193nm ASML immersion scanner with Quasar illumination mode. The typical detectors used here were necking (detected when the CD line was smaller than 47nm) and bridging (detected when the CD space was <55nm).
MBMs can be simply transferred to the Tachyon system, where the values for each mask area are read and dynamically applied to each specific mask area during the verification runs. Individual bias settings can be set on a grid as small as 20μm. For this study, numerous maps were generated and tested on 45nm gate levels. In each case, the post-OPC data was run through the nominal verification loop, and then the verification was repeated, incorporating the MBMs. All verification detector settings were left at the nominal STMicroelectronics’ Crolles 45nm production settings.
STMicroelectronics’ current OPC verification procedure for the 45nm gate process requires using a + and - 5nm (wafer scale) “pushed bias” offset to simulate the effects of potential mask CD errors on wafer printing. These values have been chosen to represent the worst possible CD deviation coming from the mask. This procedure has been proven to accurately predict potential mask CD errors. However, it can also predict tens of thousands of errors that will never actually occur with the final actual mask print results.
Three types of Tachyon LMC runs were performed in this study. LMC run 1 was the base standard production detector settings and conditions (including the +1.5nm and -1.5nm forced biases). LMC run 2 was exactly the same as the first run with the exception of adding the MBM as the starting point for the +1.5nm and -1.5nm forced biases. LMC run 3 was the same as run 2 except the pushed bias was removed, leaving the MBM as the only bias variable.
MBM results: gate 45nm
In this section, we examine the results of data gathered using the current pushed bias procedure, versus using the MBM for hot spot verification. We began with the MBM created from the first gate 45nm example (gate A) [3]. As described previously, the discrete CD measurements nominally used to certify the reticle were subtracted from the intended CD values, and the differences were then fitted into a 3D smoothed surface (Fig. 3). The values shown are differences in reticle scale. Table 1 shows the results of runs 1 and 2 (pushed bias only, and pushed bias with MBM).
 Figure 3. MBM gate 45nm “A.” |
This particular mask has an overall positive bias, so we would expect that adding more pushed bias would increase the number of bridge defects. As seen in Table 1, run 2 resulted in 47% more bridge defects and 73% fewer necking defects, which shows that MBM verification works in combination with pushed bias values. As a general tendency, the bridging hot spots simulated with the pushed bias in combination with MBM were 6nm more critical at wafer scale compared to those simulated with pushed bias only.
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The next step was to remove the pushed bias, taking into account only the real mask effects with MBM. All results shown were done by overlaying the wafer SEM images with the predicted contours created during the LMC runs.
 Figure 4. Better hot spot accuracy with LMC run 3 (MBM only). |
Better accuracy of the detected hot spots. Figure 4 shows an example where the pushed bias LMC run 1 predicted a 50nm bridge hot spot. However, the real MBM LMC run 3 predicted a 66nm potential bridge, which was more accurate, as shown by contours overlaid with the wafer SEM images.
Better filtering of false hot spot detection. Having proven the better accuracy and matching of the hot spot signature using MBM, we compared the results of the new LMC run with only the MBM. Table 2 shows that the pushed bias method resulted in almost 3 million potential hot spots. In contrast, the MBM run predicted zero hot spots, which was confirmed at wafer level through examination of a focus exposure matrix.
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We performed a second 45nm gate mask test (Gate B) comparing pushed bias versus MBM only. Again, a better filtering of the hot spots and better matching of the contours was achieved with the LMC run that used only MBM, as confirmed with wafer results (Table 3).
In this test, the pushed bias is far over-predicting hot spots. Gate B has an overall negative mask bias CD offset. Figure 5a shows one example of a necking hot spot being incorrectly predicted, while Fig. 5b illustrates the accurate prediction from MBM.
Again, we were able to perform a verification LMC run closer to real wafer finite element method (FEM) results by applying only the MBM input. Figure 5b shows an example of better filtering of the false defects and a more accurate review of the hot spots that really matter. As shown in Table 3, the LMC run with only MBM detected just 11 necking hot spots. Only one of these hot spots was verified true with FEM analysis. The forced bias method, however, predicted more than 93,000 hot spots.
Conclusion
This study demonstrates the benefits of using MBMs in OPC hot spot verification loops. We plan to put MBM into the production flow for numerous critical levels, where appropriate. LMC review with MBM showed better accuracy of the contour predictions and better conformity with the wafer SEM images. SEM measurements and predicted contour measurements for LMC runs showed only 2nm of difference with MBM, compared with an average 8nm difference for simulations without MBM.
For gate level, we once again see that LMC review with only MBM showed closer conformity to the wafers’ actual SEM images. By removing the pushed bias of the detectors and replacing the bias condition with a function of only the real effect of the MBM, we were able to filter false hot spots. On two gate runs, the number of hot spots dropped from several millions of occurrences using pushed bias to near-single digits when only the MBM was applied. This saves LMC review time and helps us to focus on the real hot spots requiring special attention on-wafer.
As illustrated in Fig. 1, a new verification loop using only MBM offers a simpler, more effective way to avoid over-prediction of hot spot signatures. This study suggests two significant benefits of model-based mask verification: more accurate hot spot detection, and better filtering of false detections. Applying only the MBM should result in more accurate predictions of the actual wafer results.
Acknowledgments
This paper couldn’t have been completed without the support of Tony Vacca, Shogo Narukawa, and Laurent Depré. Thanks also to Boris Vanderwalle for the wafer SEM images and to the Crolles RET team for their advice.
Lithography Manufacturing Check (LMC) Tachyon is a trademark of Brion Technologies.
References
- F. Foussadier, F. Sundermann, A. Vacca et al., “Model-Based Mask Verification,” Proc. of SPIE Vol. 6730, November 2007.
- F. Sundermann, F. Foussadier et al., “Model-Based Mask Verification on Critical 45nm Logic Masks,” Proc. of SPIE Vol. 7028, April 2008.
- B. LeGratiet et al., “Process Control for 45nm CMOS Logic Gate Patterning,” Proc. of SPIE Vol. 6922-33, February 2008.
Frank Sundermann received his diploma in optical physics from the French U. of ENSPG (Ecole Nationale Supérieure de Physique de Grenoble) in Grenoble, and is the mask staff engineer at STMicroelectronics, 850, rue Jean MONNET 38926 Crolles, France; ph +33 6 30 48 15 48; e-mail [email protected].
Jim Wiley received his BS in photographic sciences and instrumentation from Rochester Institute of Technology and is the senior technical director at Brion Technologies, 4211 Burton Dr., Santa Clara, CA 95054 USA; ph 408/653-1500; e-mail [email protected].
Naoya Hayashi received his BS in applied chemistry and MS in electric chemistry from Tokyo Institute of Technology and is a research fellow of electronic device operations at Dai Nippon Printing Co., 2-2-1 Fukuoka Fujimino, Saitama, Japan; ph +81-49-278-1680; e-mail [email protected].
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