High-k goes to production, but arguments continue
07/01/2008
The manufacturing infrastructure for high-k stacks is reasonably mature. Manufacturers have access to the toolsets and precursors they need, even if they aren’t sure thus far what structure to build. On the reliability front, however, much work remains to be done.
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The problem is familiar by now: As transistors shrink, they require thinner and thinner gate dielectrics. Using SiO2, even with added nitrogen to increase the dielectric constant, allows unacceptable levels of gate leakage. Instead, manufacturers are turning to new, high-dielectric constant insulators. These in turn require the replacement of polysilicon with metallic gate electrodes. The change has been described as the most radical shift since silicon replaced germanium at the center of the semiconductor industry.
At Intel, high-dielectric constant (k) gate stacks are already old news. The company proudly advertises its “hafnium-infused” Centrino products, while leading-edge development looks elsewhere. Yet elsewhere in the IC industry, high-k gate stacks still inspire a great deal of debate. According to Glenn Wilk, ASM’s product manager for transistor products, making low leakage transistors with high-k dielectrics was the easy part. Actually integrating these materials into a high-yield, reliable, cost-effective CMOS process has been far more difficult.
When to build the gate?
The search for a high-k integration scheme has been shaped by the need to balance device performance against process simplicity. Simpler integration schemes generally give more consistent performance, require fewer process steps, and cost less. Unfortunately, Serge Biesemans, IMEC’s director of CMOS technology, said they also tend to give less impressive results on one or more key parameters. Among the most striking examples of this trade-off is the difference between gate first and replacement gate processes. In a gate first process, the gate stack is fabricated before the source/drain implants and anneals. Alignment of the junctions depends on spacers, which in turn use the gate stack for alignment. The gate first approach is used for SiO2 dielectrics with polysilicon gate electrodes. It works well with those materials and is extremely familiar to the industry. Yet SiO2 is thermally and chemically stable, able to tolerate almost any annealing conditions that the wafer itself could survive. Hafnium-based gate stacks are much less forgiving. In hafnium-based gate stacks, both the dielectric and the metal electrode have thermal budgets of their own. For instance, a thermal SiO2 interlayer usually separates the wafer from the hafnium-based dielectric. During annealing, further SiO2 growth can occur at this layer, increasing the structure’s equivalent oxide thickness (EOT). Regrowth is one reason while scaling the dielectric thickness is difficult in gate first structures.
Meanwhile, the metal electrodes can react with the dielectric at high temperatures. Both tungsten and molybdenum have the work function needed for band-edge pMOS devices, Wilk said, but these metals are not thermally stable. Interactions between the metal and the dielectric can cause an unacceptable threshold voltage shift, degrading device performance. Since manufacturers cannot avoid high temperatures entirely, they must find an integration scheme that protects the gate stack during dopant activation.
The need to reduce the thermal load on the gate stack is helping to boost interest in laser annealing. Laser annealing has often been considered a way to achieve full activation with minimal diffusion, preserving ultrashallow junctions. At December’s IEEE Electron Device Meeting (IEDM), S. Kubicek and colleagues at IMEC demonstrated the use of laser annealing to achieve low threshold voltages in a gate first high-k process [1].
Intel, the first company to implement high-k gate stacks in production, appears to use one of the most radical solutions to the problem: Deposit the gate last, after the high-temperature annealing steps. Without exposure to elevated temperatures, thermal stability is no longer an issue and many different gate metals can be used. Yet the gate last approach poses significant engineering challenges. In gate last schemes, a sacrificial structure–usually polysilicon–aligns the source/drain spacers, then is removed and replaced with the desired gate stack. In a full replacement gate scheme, the sacrificial material substitutes for both the metal and dielectric layers. Although Intel has not disclosed all the details of its process, the company appears to use a more conservative partial replacement, depositing the dielectric layer first, with only a sacrificial metal layer (Fig. 1). In either case, however, the process must completely remove the sacrificial layer, then deposit two different gate stacks into trenches that narrow with each process generation. As the gate stack contains the most critical interfaces in the transistor, etch damage, poor etch selectivity, and incomplete removal of the sacrificial material can all have catastrophic consequences. While EOT scaling can be difficult for gate first schemes, gate length scaling is difficult for gate last schemes.
 Figure 1. Intel’s 45nm transistor with high-k dielectric and metal gate. Image courtesy of Intel Corp. |
While gate last processes avoid thermal stability issues, some gate first processes meet the challenge head-on, using noble metals such as ruthenium or platinum. Noble metals are extremely difficult to etch, posing substantial integration challenges. Even so, these materials can also suffer thermal degradation. As C. S. Park and coworkers at Sematech noted at this year’s VLSI Technology, Systems, and Applications symposium (VLSI-TSA), a key challenge for ruthenium-based gates is stabilization of the ruthenium oxide layer at the dielectric interface. After annealing, the work function for ruthenium oxide shifted toward mid-gap values. The addition of aluminum appears to help stabilize the stack [2].
Both gate first and gate last processes struggle to meet the challenges of manufacturability, scalability, and performance. Yet the history of the semiconductor industry is littered with seemingly intractable problems that were eventually solved by the emergence of a third alternative. When faced with the need for a thermally stable metal with a band edge work function, one alternative is to change the work function target.
Hafnium, and what else?
Manufacturers have learned that inserting a cap layer between the dielectric and the metal allows them to achieve the desired threshold voltage with a much wider range of metal electrodes. Although cap layers bring additional deposition steps, additional interfaces, and additional materials compatibility issues, they appear to be the best way to bring acceptable metal choices to gate first processes.
Cap layer schemes generally use lanthanum oxide in nMOS gate stacks, and aluminum oxide in pMOS gate stacks. It can be misleading to treat these materials as discrete layers, however. As lanthanum oxide in particular is an aggressive silicate former, Paul Kirsch and coworkers at Sematech suggested that lanthanum may seek out the SiO2 interlayer [3]. Fully removing lanthanum oxide from the pMOS regions is challenging, but any oxide left behind will degrade the pMOS threshold voltage. The IMEC group [1] found that very low threshold voltages could be achieved with a 1.0nm La2O3 cap layer, but carrier mobility degraded significantly. Thinner cap layers gave less mobility degradation, but larger Vt values. They observed similar behavior in pMOS transistors with an Al2O3 cap layer.
The IMEC work raises another important question as well, regarding the exact composition of the hafnium-based dielectric layer. Should it incorporate silicon, nitrogen, both, or neither? Adding nitrogen increases the dielectric constant, helping with EOT scaling, but it doesn’t necessarily improve other performance parameters. In pMOS transistors, leaving nitrogen out improved both mobility and threshold voltage. The IMEC group achieved band edge work functions and low threshold voltages using an HfSiON/La2O3 stack with Ta2C for nMOS transistors, and an HfSiO/Al2O3 stack with TaCN metal for pMOS devices. Incorporating silicon into the dielectric appears to reduce interface defects, an important consideration for low-power devices with strict gate leakage constraints. Kirsch found that thick HfO2 layers tend to crystallize [3]. Adding silicon during deposition suppresses crystallization, avoiding grain boundaries, dislocations, and point defects. Unfortunately, silicon also reduces the dielectric constant, limiting scalability to low EOTs. In general, Wilk said, high-performance devices are likely to use HfO2 to achieve the highest possible dielectric constant. Low-power devices need high-quality, low-leakage interfaces, and tend to add silicon.
With so many different trade-offs to consider, it’s not surprising that, according to Biesemans, more than 15 different gate first integration schemes have been seriously considered. The complexity of even the simplest hafnium-based gate stacks substantially slows process optimization and extends learning cycles. To evaluate an integration scheme, researchers first must identify a full set of etch processes, screening each potential chemistry for selectivity. Without selective etching, it’s impossible to even complete test structures for the proposed integration scheme, much less compare it with alternatives. As a result, learning cycles can take six months or more.
Putting the pieces together
In part because progess is so slow, it’s still impossible to define a gate first reference process. Most schemes agree on a few key elements, however. First, grow a very thin oxide interlayer, with or without incorporated nitrogen. Deposit a hafnium-based dielectric (with or without silicon and/or nitrogen) on top of it. Deposit the lanthanum oxide cap layer on top of that.
According to Wilk, ALD is typically used for dielectric deposition. This technique, being surface-limited, gives the precise thickness control needed when the desired EOT is on the order of a nanometer. ALD deposition of cap layers has been problematic, however. Both lanthanum oxide and aluminum oxide are deposited from solid precursors, raising the risk of clogs and contamination. (See also “ALD comes to single-metal high-k gate stacks,” WaferNews, 5/27/08.) PVD, the usual deposition method, risks sputtering damage to the exposed hafnium oxide surface. Worse, PVD requires a different process chamber, and perhaps even a different process tool. Breaking vacuum between the dielectric and the cap layer raises the risk of contamination and interface damage. ASM’s recent announcement of ALD processes for both lanthanum and aluminum oxides suggests that these issues have now been resolved.
After lanthanum oxide deposition, patterning of the resulting stack defines the nMOS device regions. The patterning step represents one of the main integration debates. If the same dielectric is used for both nMOS and pMOS, then the etch should remove the excess lanthanum oxide only, stopping without damage to the underlying hafnium oxide. If not, then the etch must remove the hafnium-based layer as well. This latter path, like the replacement gate scheme, risks damage to the SiO2 interlayer and the underlying channel. These interfaces are the most critical in the entire device structure. The more material is removed during the etch step, the more challenging it can be to preserve vertical sidewalls and prevent damage to the unpatterned portions of the device. Many process integration schemes use a hard mask to maximize selectivity.
After patterning and removal of the hard mask (if needed), the next step deposits the pMOS dielectric (if different from the nMOS dielectric) and then the aluminum oxide pMOS cap layer. A second patterning step removes these materials from the nMOS regions. The result should be a more or less planar structure in which the nMOS and pMOS stacks meet in the shallow trench isolation regions. If one metal is used for both devices, it is deposited now, and a final patterning step creates the isolated towers that will become the gate stacks for the finished transistors. Dual metal structures would require an additional patterning, etch, and deposition sequence for the second metal.
 Figure 2. Single metal, dual dielectric CMOS process flow. Note that the nMOS “cap” is located below the high-k material. Patterned using 248nm photoresist [4]. |
Within this sequence, nearly endless variations are possible. One scheme, proposed by T. Schram and coworkers at IMEC at the VLSI Symposium in June, actually places the lanthanum oxide cap layer under the high-k dielectric (Fig. 2). Patterning, with a dilute HCl solution, doesn’t damage the hafnium oxide because it doesn’t exist yet [4].
High-k still not solved
Although high-k dielectrics have been anticipated for 10 years, they are only just entering production at the 45nm technology generation. Most manufacturers are unlikely to insert these materials before the 32nm generation. Yet over the last 10 years, as manufacturers have struggled to work within the limitations of silicon-based dielectrics, they have turned to a wide range of mobility enhancement techniques. Some of these may actually help with high-k integration as well. Sematech’s Rusty Harris explained that the threshold voltage depends on the difference between the work function of the metal and that of the underlying semiconductor. Germanium, under consideration as a high-mobility alternative channel material for pMOS devices, also happens to have a different work function from silicon. The Sematech group demonstrated gate first integration of an HfSiON dielectric and TiSiN metal (no cap layer) with a SiGe-channel pMOS transistor [5].
As this article has shown, gate first high-k integration has yet to coalesce around a single consensus approach. Still, as Sematech program manager Paul Kirsch explained, the manufacturing infrastructure for high-k stacks is reasonably mature. Manufacturers have access to the toolsets and precursors they need, even if they aren’t yet sure what structure to build. On the reliability front, however, much work remains to be done. Advanced dielectric stacks contain at least two, and often three, distinct materials, Kirsch said. The resulting structure may behave as a single layer, or each material may have distinct breakdown characteristics. Circuit reliability models are not yet prepared to handle a “partial breakdown” of one component layer in such a stack. Before the industry can have the same confidence in high-k gate stacks that silicon dioxide inspires, researchers will need to develop better models and a better understanding of the underlying physics of these materials. High-k gates have come a long way, but still have much further to go.
References
- S. Kubicek et al., “Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal,” IEDM Tech. Dig., 2007.
- C.S. Park et al., “Achieving Low Vt (<-0.3V) and Thin EOT (~1.0nm) in Gate First Metal/High-k pMOSFET for High Performance CMOS Applications,” Proc. VLSI-TSA (2008), pp. 154-155.
- P.D. Kirsch et al., “Band Edge n-MOSFETs with High-k/Metal Gate Stacks Scaled to EOT=0.9nm with Excellent Carrier Mobility and High Temperature Stability,” IEDM Tech. Dig., 2006.
- T. Schram et al., “Novel Process To Pattern Selectively Dual Dielectric Capping Layers Using Soft-Mask Only,” VLSI Tech. Symp. (2008). In press.
- H. Rusty Harris, “Band-Engineered Low pMOS VT with High-k/Metal Gates Featured in a Dual Channel CMOS Integration Scheme,” VLSI Tech. Dig., 2007, pp. 154-155.
In 2001, Katherine Derbyshire founded Thin Film Manufacturing, a consulting firm helping the industry manage the interaction between business forces and technology advances. She has engineering degrees from the Massachusetts Institute of Technology and the U. of California, Santa Barbara. She can be reached at [email protected].