Issue



32nm node USJ formation using rapid process optimization metrology


07/01/2008







Ultra-shallow junctions (USJs) that are <10nm at the 32nm node require the close process optimization of ion implantation (elemental species, energy and dose) with diffusion-less annealing (millisecond and spike combination) in order to reduce device variation and achieve “high-quality” junctions. Such high-quality junctions must have high dopant activation, low junction leakage, and stable residual implant defects after anneal to prevent subsequent dopant deactivation. USJ process optimization can require many different wafer split lot testing, but fortunately, through the use of rapid process optimization metrology, we can run many process variations and get quick junction quality results within a few hours using non-contact optical metrology techniques. These metrology techniques also provide global and localized wafer micro-uniformity detection revealing the unique uniformity signatures of each different ion implanter and annealing equipment needed to reduce device variation.

Sub-10nm USJs will be required for manufacturing starting at the 32nm node. Usually, such shallow junctions can be realized using deep pre-amorphous implant (PAI) layers, such as Ge, to eliminate boron channeling and to enhance dopant activation for B, BF2 , and As (<2keV), resulting in impressive sheet resistance (Rs) versus Xj junction depth values [1-4]. However, using Rs only as a metric for USJ “goodness/quality” can be misleading, resulting in very leaky junctions and in the wrong optimized USJ process. After diffusion-less dopant activation annealing, the residual implant damage/defects caused by the PAI amorphous layer can lead to end-of-range (EOR) damage beyond the junction, thereby degrading junction leakage resulting in “poor-quality” junctions. This was the motivation of the work back in 2002 reported by Borland [5,6] and Matsuda of NEC [7], as well as Severi of IMEC [8] in 2004.


Figure 1. Effect of PAI EOR damage location on junction leakage degradation [5-8].
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If the EOR damage is located within the junction, then good junction leakage current was realized as summarized in Fig. 1 [5-8]. Note that a 10nm change in EOR damage depth can degrade junction leakage current by one to two orders of magnitude (Fig. 1). Therefore, measuring junction leakage current and also residual implant damage after anneal are important parameters that must also be measured to determine USJ junction quality as reported by Borland [9-13] and Mineji [14], while Duffy [15] reported on the added leakage degradation effects of HALO dopant level, which must also be optimized.

Unstable defects due to incomplete implant damage annealing during msec annealing can also be a problem as reported by Moroz of Synopsys at the MRS March 2008 meeting [16]. For example, he reported that defects from >10keV Ge-PAI implants are hard to anneal with msec-only anneals and require either 1) multiple repeat msec anneals (i.e., up to 10 laser scan anneals [Lerch reported up to four repeated Flash anneals] [17]); 2) spike anneal >1000??C; or 3) using C, F, or N co-implants to trap the excess interstitials. He stated that residual implant damage results in dopant deactivation or provokes junction leakage.


Figure 2. Effects of msec peak temperature and post spike anneal on the formation of {311} stable defects [18].
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In another paper at the MRS meeting (Camillo-Castillo of Univ. of Florida [18]), researchers compared shallow to deep Ge-PAI, 8keV (PAI~15nm) vs. 30keV (PAI~47nm) with increasing Flash (fRTP) temperatures. They further observed that increasing the temperature from 1100??C to 1300??C reduced defect density by >30?? (from 2E11 defects/cm2 to <6E9 defects/cm2) for 30keV Ge-PAI, and >1000?? (from 2E11 defects/cm2 to <2E8 defects/cm2) for the shallower 8keV Ge-PAI, and the dot-like defects evolved to stable {311} dislocation loops at 1300??C (Fig. 2a-c). They also showed that for the lower fRTP temperature of 1100??C, stable {311} residual defects can be obtained by adding a post 950??C spike anneal (Fig. 2d). From cross-sectional TEM, no defects could be seen for the 8keV Ge-PAI due to surface recombination of the defects.

Similar observations were reported by Noda of IMEC at the SSDM 2007 meeting [19] comparing Ge-PAI at 5keV, 8keV, and 30keV with B 500eV using DSA (dynamic surface anneal) laser annealing from 1000??C to 1300??C. Stable {311} dislocation loops were formed for only the very high temperature 1300??C anneal. They also noted that for the shallow 5keV Ge-PAI process, all the end-of-range (EOR) defects were gone after the 1300??C anneal due to the shallow amorphous layer of <9nm. This effect was first reported independently in 2004 by Mineji of Selete [20] and Surdeanu of Philips/IMEC [21], where they showed the disappearance of EOR defects if the amorphous layer was <8nm from the surface.

Combination anneals for stable defect formation

To achieve stable defects with msec only anneals requires peak temperatures >1300??C so temperature calibration between each msec annealing equipment is needed. Borland has shown that peak temperature differences between the various Flash (Arc-lamp fRTP or Xe-lamp FLA [flash lamp anneal]) and laser spike anneal (LSA) or dynamic surface anneal (DSA) equipment can vary significantly from a low of 1175??C up to the silicon melting temperature of 1407??C [22]. Lower msec anneal peak temperatures result in incomplete implant damage annealing, requiring the combination of a low temperature diffusion-less spike anneal or multiple msec anneals [11,16-18]. Moroz reported the spike temperature needs to be >1000??C [16], while Camillo-Castillo reported that a 950??C spike temperature works in forming stable defects (Fig. 2d) [18].

Using RsL junction leakage metrology, Borland observed that with a 10keV Ge-PAI process and 15nm-deep junctions, a 900??C spike anneal also works, improving junction leakage by 1000??, which results in complete implant damage anneal [11]. Additionally, such an anneal is also diffusion-less as detected by SIMS [14]. With msec FLA only anneal, the 10keV Ge-PAI+B had the lowest Rs value of 498 ohms/sq., but due to the deep PAI EOR damage, >18nm deep, the junction leakage current (Io) was 1.3E-4A/cm2 (very leaky) compared to the B500eV/1E15 junction, which had an Rs value of 2013 ohms/sq. and Io is <1E-7A/cm2. The 10keV B18H22 implant had an Rs value of 751 ohms/sq. and also very good junction leakage current Io is <1E-7A/cm2 due to the absence of EOR damage. The detailed explanation was first reported by Borland at IWJT 2006 [9].

Adding a 900??C spike anneal before FLA improved both the global and localized micro-variation by ~3?? as reported by Borland at IWJT 2007 [11], and also resulted in complete implant damage annealing, including EOR damage so the Ge-PAI+B Io was now <1E-7A/cm2. TW analysis detection of defect stability was measured and FLA TW=550, while 900??C spike+FLA TW=116. Very recent results for a 900??C spike+FLA vs. a FLA+900??C spike annealing sequence were reported by Borland and Kiyama at the June 2008 Ion Implant Technology conference [23] at a 32nm node using B200eV/1E15 for <8nm USJ and 5keV Ge-PAI (9nm). They noted similar effects as reported by Noda [19] that the Ge+B EOR damage disappeared due to surface recombination resulting in excellent junction leakage current, Io<1E-7A/cm2, but for the 5keVGe+890eVBF2 case, the presence of F had a very negative effect resulting in the worse junction quality with a >2?? degradation in Rs from 931 to 1977 ohms/sq. and a 500?? degradation in junction leakage from 1.2E-7 to 5.4E-5A/cm2 [23].

However, for the spike+FLA or FLA+spike cases, the junction leakage was improved to <1E-7A/cm2 even for the Ge+BF2 case, but the Rs values were higher–part of this could be due to the retained dose effect for junctions <10nm as reported by Borland [24], where 25% of the BF2 dose can be lost at <8nm depth. TW analysis shows that with msec only FLA, the Ge-PAI EOR defect level is ~160, and the 900??C spike before or after FLA lowers residual implant damage to a stable TW value to <50.

Stable residual implant defect formation

As stated earlier, msec only annealing requires a temperature >1300??C for complete implant damage annealing [18], or multiple laser scans [16], or Flash anneals [17]. Using >15nm junctions formed with various boron and PAI implants (500eV B, 2.5keV BF2, or 10keV B18H22 implants and Ge-PAI at 5keV, 10keV, and 20keV), Kawasaki of Renesas reported the comparison between diffusion-less SPE and different LSA (laser spike anneal) power levels at IIT 2008 [25]. With LSA, six different laser power settings were studied on the same wafer for rapid process optimization using the high-resolution capabilities of RsL and TW in the full wafer mapping mode and diameter line scan mode.


Figure 3. High-resolution RsL sheet resistance line scan and wafer map of the 500eV B wafer revealing the six different laser power level areas and the Rs varied from 2116 to 432 ohms/sq.
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Figure 4. High-resolution TW line scan and full wafer image showing TW of 327 in the unannealed areas and varied from 225 to 25 in the different annealed regions.
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Figure 3 shows the RsL line scan and wafer map for the 500eV B implant with six different LSA scanned power setting areas and Fig. 4 is for the TW results of the same wafer. The Rs value improved from 2116 ohms/sq. for power level 1, to 432 ohms/sq. for power level 6, representing a 5?? improvement. The laser beam is 6mm and each scan power level area is 30mm, so 10 scans per area with a 50% overlap resulting in 3mm overlap width and the TW line scans clearly detected each laser beam scan and overlap stitching region as shown in the blowup image of Fig. 4. In the un-annealed regions of the wafer, the diameter TW scan shows the as-implanted damage regions have a TW value of 327, while in the scanned power level 1 area, the TW signal varied from 175 to 225; and in the scanned power level 6 area, the TW signal was ~40, but the lowest TW signal was in the scanned power level 4 area, which was 25, so the implant damage recovery with annealing can be clearly detected by the TW line scan in Fig. 4. The TW blowup of the LSA power level 1 area reveals the expected 3mm laser stitching pattern in the y-direction due to the 3mm 50% overlap step between each x-direction scan, and the TW variation is ~25%. What is also very interesting is the TW detection of a 1mm micro-variation in the x-direction of ~7%. It is speculated that this is the signature of the spot beam implanter.


Figure 5. Rs result comparison.
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The complete RsL sheet resistance results for the complete test matrix are shown in Fig. 5, while the RsL junction leakage results are shown in Fig. 6, and the TW results in Fig. 7. Based on the Rs results, the lowest values for all the different LSA power levels occurred with the deepest 20keV Ge-PAI process, followed by the 10keV process. As shown in Fig. 7, all these junctions are very leaky, and therefore optimizing the USJ implant and msec annealing process based only on Rs would be very misleading and would result in poor, leaky junctions, thereby making these Rs results questionable. These results are similar to those reported by Borland [11] and illustrate why looking at junction quality, and therefore leakage current and defect stability, are very critical when developing USJ processes with diffusion-less annealing. The 20keV Ge-PAI wafers had the worse junction leakage current with a degradation of ~1000?? to E-4A/cm2 levels compared to E-7A/cm2 without Ge-PAI for LSA power level 1 annealing.


Figure 6. Leakage result comparison.
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If the requirements for a high-quality junction were Rs<1K ohms/sq. and leakage <1E-6A/cm2, then for LSA power levels of 1 and 2 (estimated peak temperature of <1150??C), B18H22 is the only dopant of choice, but for power levels 5 or 6 (estimated peak temperature of >1325??C), then B18H22, BF2, B, and 5keVGe-PAI+B would all meet that criteria, while the 10 and 20keV Ge-PAI process would not. With SPE annealing only, B18H22 resulted in a high-quality junction with very low junction leakage. Figure 7 shows the TW technique’s ability to detect incomplete implant damage annealing, which is evident for the low LSA power levels where the TW value is >100. At the higher power levels, the TW values dropped to 25-50, suggesting completely annealed and stable residual implant damage.


Figure 7. TW result comparison showing when implant annealed stable defects are realized.
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One of the critical manufacturing concerns at the 32nm node is reducing device variability. Electrically active dopant variation in the device can directly be caused by micro-uniformity variation in implantation and annealing [13].

Implant uniformity: With diffusion-less annealing techniques, the implant micro-uniformity variation will directly impact localized device variation. With TW analysis, these implanter micro-uniformity variations can clearly be detected as reported by Borland [13]. After annealing, the non-uniformity of the annealer can dominate uniformity, thereby washing out the implant variation effects so improvements in diffusion-less anneal uniformity are critical and a first priority [11].

Annealing uniformity: Similar to detecting the implant micro-uniformity variation, the TW wafer image and line scan can also be used to detect diffusion-less msec and spike annealing micro-uniformity variations [11-13,22,24] for FLA, fRTP, LSA, and DSA. (See Fig. 4 for an example for LSA.) The wafer global and local uniformity variation with msec only anneal can be improved significantly with a diffusion-less 900??C spike anneal [11]; so the 900??C spike anneal provides another benefit besides defect stabilization: It also improves Rs uniformity, eliminating the msec annealer poor uniformity effects, so calibration between Rs and TW micro-uniformity to reduce device variation is important.

As stated earlier, the best USJ process for dopant activation (low Rs) may degrade other junction properties such as leakage. The same is true for process integration. The best USJ process can also cause strain-Si relaxation and gate stack degradation leading to trade-offs in the process integration flow.

Strain relaxation (eSiGe and eSiC): Another process integration concern is strain-Si relaxation caused by the high-temperature msec annealing step especially with eSiGe. Relaxation has been reported by Hoyt to start at temperatures above 1000??C with LSA [26], while Hoffmann reported 35% relaxation with DSA laser annealing [27]. To reduce this effect, Yamamoto of Fujitsu [28] reported lowering the LSA temperature by over 100??C to <1200??C, so a trade-off between junction quality (dopant activation and junction leakage) and strain-Si relaxation must be made. The compromise in dopant activation at the lower msec annealing temperatures of <1200??C can be corrected with a deep Ge-PAI, but junction leakage would limit the depth to <10keV if combined with a diffusion-less spike anneal.


Figure 8. Effects of adding HALO dose and Ge-PAI on junction leakage degradation.
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Gate stack formation: Diffusion-less annealing sequence and process optimization are also dependent on the gate stack structure. With doped poly gate electrode over SiON or Hf-oxides and gate first process flow, the poly must be fully doped before the diffusion-less msec+spike annealing sequence, because neither msec anneal nor the diffusion-less spike anneal for defect stabilization will diffuse the dopant through the thick poly resulting in incomplete poly gate dopant activation and poor Tinv. The only two options are either: 1) poly pre-doping as reported by Narihiro of NEC [29], or 2) a disposable spacer process using a high-temperature spike diffusion anneal after deep S/D implant to fully dope the gate poly followed by dummy spacer removal and HALO/extension implants and finally msec anneal as reported by Eiho [30]. The leakage issue with HALO/extension implants will be discussed in the next section. With gate last processing, there are no issues with the msec anneal USJ process sequence since there is no poly doping required, as reported by Mistry of Intel [31].


Figure 9. Trade-offs in annealing method and technique on junction leakage.
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Junction leakage HALO effects: The importance of measuring USJ junction leakage current with diffusion-less annealing was shown in Figs. 1 and 6. But if you add the effects of HALO dose (doping level) with Ge-PAI, junction leakage degrades by an additional several orders of magnitude (Fig. 8), further complicating process optimization [7,15,21,32]. Note that increasing the HALO dose from 2E13/cm2 to 4E13/cm2 with spike anneal degrades junction leakage by an order of magnitude. With msec flash only anneal, a 2E13 HALO dose has an order of magnitude higher leakage than spike, and at a 4E13 dose, it is 500?? worse. Adding Ge-PAI with HALO and flash anneal only results in leakage that is ~100?? worse. However, increasing the flash peak temperature by 50??C from 1250??C to 1300??C will also improve leakage by 10?? (Fig. 9); in a similar way, Figs. 2b and 2c show the reduction in EOR damage and the formation of stable defects. Increasing the intermediate temperature to 800??C also improves junction leakage by 10??. Therefore, using B18H22 rather than Ge-PAI+B may be the best option overall for p-type USJ. For n-type USJ both phosphorus and antimony are being studied right now as a replacement for arsenic at the 32nm node, and more comparison results will be reported in the future.

Conclusion

Rapid process optimization metrology techniques are critical for 32nm node ultra-shallow junction process development when using diffusion-less anneals. Besides sheet resistance, junction leakage current and defect stability are also important for high-quality junctions. Using RsL and TW, we were able to get quick process feedback to optimize the process and realize <10nm p+ and n+ USJs with HALO for various gate integration sequences and strain-Si technologies.

Acknowledgments

The authors are grateful for the support they received from Iad Mirshad, Mira Bakshi, Alex Salnik, and Lena Nicolaides of KLA-Tencor. Thanks also to Haruo Akimito and Vladimir Faifer of Frontier Semiconductor.

References

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John O. Borland received his BS and MS from MIT and is the founder of J.O.B. Technologies, Aiea, HI USA; e-mail [email protected].

Yoji Kawasaki received his MS from Kanseigakuin U. in Japan and is a manager in the diffusion technology group at Renesas Technology Corp., 4-1, Mizuhara, Itami-shi, Hyogo, 664-0005, Japan; e-mail [email protected].

Jeffri Halim received his BS from UC Berkeley and is an applications engineer at Frontier Semiconductor, 199 River Oaks Parkway, San Jose, CA 95134 USA; e-mail [email protected].

Brian Chung received his BS from Cal State Polytechnic U. and is a marketing manager at KLA-Tencor, 160 Rio Robles, San Jose, CA 95134 USA; e-mail [email protected].