Temporary bonding/debonding for ultrathin substrates
07/01/2008
A jointly developed temporary bonding/debonding system designed for ultrathin wafer processing is described, as well as critical parameters to be considered in processing thin wafers, including TSV creation.
A number of industry drivers are necessitating handling and processing of thin to flexible substrates for standard semiconductor and packaging process equipment. Chief among these is shrinking form factor, driven primarily by handheld consumer electronics such as cell phones, music players, cameras, and game systems. To accommodate these products’ manufacturing demands, thinning of device wafers has become common. The use of through-silicon via (TSV) technology has been proposed to enable further reduction of package footprint and increase capacity and functionality, but the flexibility and fragility of ultrathin device wafers, which tend to warp and fold, necessitate a support system to make TSV processing on traditional equipment viable.
EVG and Brewer Science have worked jointly to develop a solution that enables temporary bonding of a device wafer to a rigid carrier substrate, allowing not only thinning but also a full range of processes, including high-temperature deposition, etching, lithography, dielectric application, and curing, plating, and chemical cleaning steps on the thinned substrate by using existing and established processes and equipments. This article examines critical parameters to be considered in processing thin wafers, including TSV creation, provides an overview of temporary bonding techniques, and offers details of the jointly developed temporary bonding/debonding system and its benefits.
TSVs: Solution and challenges
TSVs are becoming increasingly important as the industry strives to cope with device manufacturing challenges caused by trench and via variability (both depth and profile), as well as wafer-thinning processes. These vertical electrical connections pass completely through a silicon wafer or die, enabling chip-to-chip interconnect schemes compatible with 3D wafer-level packaging and 3D integrated circuits. TSVs enable size reduction in all three dimensions, as well as much shorter interconnect lengths between device components–in turn, improving signal speed and reducing parasitic power consumption. The structures needed to provide these advantages require a full range of semiconductor and packaging processes on wafers with thicknesses from just a few up to 100 microns.
The use of temporary bonding and debonding techniques utilizing a carrier wafer to provide sufficient mechanical support is the most common handling solution for thin and ultrathin wafers. Once the device wafer is temporarily bonded to the carrier wafer, it is back-side processed, including thinning, TSV processing, or metallization. After completion of the back-side processing steps, the device wafer can be easily released from the carrier wafer and proceed to final packaging processes.
Temporary bonding basics
A typical process flow for temporary bonding involves fully processing the device wafer on the front side. The carrier wafer and/or the device wafer is coated with a spin-on adhesive, and both wafers are then transferred to a bond chamber, where they are carefully centered and vacuum-bonded at elevated temperatures. Following temporary bonding, back-side processes (thinning, etching, metallization, etc.) are applied to the wafer stack, and the thin device wafer is then debonded from the carrier wafer (Fig. 1).
 Figure 1. EVG temporary bonding/debonding process flow. |
The two main classes of intermediate materials for temporary bonding are spin-on adhesives and laminated tape. The intermediate material enables the maximum subsequent process steps and allows the widest range of parameters corresponding to these steps. The choice of intermediate material depends on three key characteristics: chemical resistance, maximum operating temperature and thermal budget, and high-vacuum/high-temperature capability.
For commercially available adhesives, there are three classes of debonding release mechanisms: thermal, UV, and chemical. The main disadvantage of chemical release is that the thin wafer floats uncontrolled in a solvent bath after debonding, which is usually incompatible with the thin wafers needed for TSV integration. With thermal release, the release temperature is higher than the maximum operating temperature, which is often incompatible with the devices’ thermal budget. And UV release materials require a transparent carrier wafer, which not only increases the cost, but also creates a situation whereby the device and carrier wafer have different thermal expansion properties, resulting in a bowed or warped stack. Moreover, the thick carrier wafer can dominate the thermal expansion behavior of the whole stack.
New approach optimizes bonding process
In late 2004, EV Group and Brewer Science began collaborative development of a system that could overcome existing tape-based or wax-based adhesives’ limitations–e.g., narrow temperature compatibility (typically <170??C) or poor TTV–and could, at the same time, allow fast and reliable debonding of the thin device wafer from the carrier, followed by residue-free removal and cleaning of the adhesive.
In developing their temporary bonding/debonding methodology, the companies considered characteristics of the carrier wafer, used to give the device wafer mechanical stability, protect the wafer edge, and prevent the thin device wafer from bending or warping. While various types of carrier wafers can be used for different applications, the most promising candidate materials are silicon and glass. In terms of the adhesive application and bonding process, no significant difference exists between the two. This is not the case when it comes to the post-bonding process steps used for TSVs. Glass and silicon can have very different coefficients of thermal expansion (CTEs). For a silicon-silicon wafer, a bonded stack remains flat, even during high-temperature process steps, enabling safe and reliable handling within existing and established equipment and production lines. In contrast, a silicon-glass wafer stack can show reasonable bow once heated up, potentially leading to significant difficulties in implementation.
Comparing their thermal properties and taking into account the high thermal conductivity of silicon, it is clear that a silicon-based wafer stack enables shorter process times for steps that involve temperature treatments. On plasma etching or sputter technology–where the energy and resulting temperature are induced onto the wafer stack from one side, leading to a temperature gradient through the wafer stack onto the bottom wafer chuck–a wafer stack with higher thermal conductivity, i.e., a silicon-based stack, enables faster process times and, therefore, enables higher throughputs.
The geometry of the wafer stack can be tailored in such a way that the stack mimics a standard wafer. A key benefit of the EVG/Brewer Science approach is that the silicon-silicon stack enables device manufacturers to use standard fab equipment for further processing. The cost for the implementation of temporary bonding/debonding technology using a rigid carrier wafer is considered to be dramatically lower than considering implementation dedicated handling technologies like thin-wafer chucks, end-effectors, and wafer cassettes on each tool, estimated by some to be as high as $500,000 per process.
 Figure 2. EV Group and Brewer Science fully integrated temporary bonding process flow. |
The result of the two companies’ work is a fully integrated temporary bonding process whereby the intermediate layer of thermoplast-based WaferBOND HT temporary adhesive material, developed by Brewer Science, is applied in liquid form via spin-coating onto either the device and/or the carrier wafer, followed by a bake step to drive out the remaining solvent from the adhesive (Fig. 2). The final bond step is accomplished in a vacuum chamber on a fully automated EVG850TB/DB temporary bonding/debonding cluster platform, where the two wafers are pressed together at elevated temperatures to facilitate a homogeneous bond, uniformly covering and encapsulating the device wafer topography.
The WaferBOND HT materials can withstand processing temperatures well above 300??C and yet enable release at 200??C or below, while the EVG850TB/DB platform can process wafer sizes up to 300mm. The flexibility and performance of the thermal-activated release technology also provide major advantages, as the carrier can be chosen that best matches the device substrate, while the debonding enables reliable release of the thin device wafer and cleaning and removal of the remaining adhesive, with minimal effort and solvent use. Taken together, these characteristics make the process viable for high-volume manufacturing (HVM) environments.
TSV formation
The many operations in the 3D integration process include through-wafer via formation using chemical etching, laser drilling, deep trench capacitor technology, via filling, deposition of diffusion barrier and adhesion layers, metallization, and wafer thinning, dicing, alignment, and bonding.
Typically, the TSV copper interconnect will be made prior to thinning of the device substrate, with the key processes of laser drilling or deep silicon etch, dielectric liner, barrier, and seed layer deposition and copper or tungsten fill conducted from the front side of the device wafer while at full thickness. In this case, the front side is bonded to the carrier substrate using WaferBOND HT materials on the EVG850TB/DB platform. This temporary carrier serves multiple purposes: It protects the front-side device structures during back-side processing, allows complete planarization of front-side topography and, once the device wafer is thinned (typically well below 100µm), provides rigid support for storing, handling, and processing of the thinned wafer. Back-side processing begins with thinning to expose the TSV interconnect–first, by grinding for fast removal of the bulk of the back-side silicon, then by polishing steps (plasma etch, chemical etch, chemical-mechanical planarization, or some combination) for the last 10-20µm of thinning.
 Figure 3. The front side of the wafer is temporarily bonded to a carrier substrate using WaferBOND HT materials for back-side processing. |
This is typically followed by dielectric passivation of the back side prior to redistribution metallization, accomplished primarily by either oxide deposition or one of a range of polymer dielectrics such as polyimide, polybenzoxazole (PBO), or benzocylobutene (BCB) (Fig. 3). For best quality and deposition rate, oxide deposition is performed at temperatures above 300??C, in high vacuum for 5-15 minutes. Polymer dielectrics require spin coat, solvent removal bake, and curing, typically at 220??C to 350??C for 30 minutes to several hours. The polymer dielectrics are usually photoimageable and require a develop process or, after final cure, application of a photoresist, followed by lithography, development, etch, and stripping of the photoresist to open the dielectric to the TSV interconnect structure. With silicon-based carriers, an EVG IQ Aligner or EVG600 Series Aligner is used to align the lithography layers through the back side of the carrier.
 Figure 4. A basic TSV production process requires approximately 22 manufacturing steps for completion. Courtesy CEA LETI MINATEC, Grenoble, France. |
Next, the seed layer is deposited if plating is used for redistribution metal or full metal deposition. In either case, these processes are typically applied in high vacuum at temperatures above 300??C. This is then followed by a lithography process to define metal lines and bond pads, either for electroplating with the seed layer or for subtractive chemical etching of the metal layer, exposing the thinned wafer-on-carrier to strong acid or base chemistries, as applicable. Following that, the dielectric passivation process is repeated to open the bonding pads that will be used to bond to a second device or to a board (Fig. 4). In many cases, the substrate will also need to survive a full solder-bumping process depending on the device-to-device or device-to-board interconnection required.
Debonding and cleaning
At this junction, there are typically two options: Debond the thinned wafer and transfer to film frame for dicing and chip-to-wafer, chip-to-chip, or chip-to-board bonding; or conduct full-wafer permanent bonding to a second device wafer, followed by debonding from the carrier. The thermal-activated debonding process consists of using a compliant chucking system to protect the newly created topography on the back side of the device wafer while heating above the softening point of the temporary bonding material.
For debonding, the wafer stack is fixed in an appropriate debond-module on both sides with a compliant chucking system, uniformly heated, and then, when the debond temperature is reached, two wafers are slid apart. The debond-module itself is designed to enable safe processing and debonding of the thin wafer from the carrier by ensuring the wafer is always fully supported on the whole area and kept flat and stress-free during the debonding procedure.
The Brewer Science HT-series temporary bonding materials have been designed to provide the necessary mechanical support at all temperatures to which they’re subjected during thinning and TSV processes. At room temperature or slightly elevated temperatures, these materials exhibit very high viscosity, whereas upon heating to the specified debond temperature, the viscosity of the polymer drops to a relatively low level and therefore allows the thinned device wafer to be separated from the carrier using full-wafer-sized vacuum chucks. The debond temperature can easily be as low as 200??C or even slightly lower, enabling per-wafer debonding to be completed within a few minutes. After separation of the wafers, the thin wafer is safely transferred to a single wafer-cleaning chamber, where the remaining adhesive is removed with an appropriate solvent. This approach allows fast, 100% residual-free adhesive removal using a minimal amount of cleaning solvent, enabling consumables and costs to be kept as low as possible.
Using a process very similar to that of spin coating, the device wafer is transferred to a wafer-sized chuck on a spin coater. A widely accepted solvent is dispensed on the device wafer (or carrier) and allowed to soak for a period of time. During the soak process, the solvent is agitated using a proprietary tool developed by EVG to better dissolve the polymer. As the polymer dissolves, the wafer is spun and sprayed with additional solvent to allow complete cleaning. A final high-speed spin is used to completely dry the wafer for transfer to the final output format. The wafer is fully supported throughout all process steps by a special end-effector or spin chuck until it is transferred to the film-frame carrier or other outputs.
Cleaning of the carrier wafer is performed with the same process and technology, further ensuring the cleaned carrier can be re-used immediately. The fully integrated temporary debonding process includes debonding of the wafer stack, cleaning of device wafer and carrier wafer, outputting the thin wafer to a defined output format, and unloading the carrier wafer to a cassette in the fully automated EVG850DB platform. Each necessary individual process module is also available in a stand-alone, semi-automated format with operator-assisted loading/unloading procedures.
Conclusion
The bonding/debonding technology that is described above enables a flexible, fast bonding scheme using carrier substrates, predominantly silicon. Debonding and further cleaning of both wafers are performed within a single piece of equipment, enabling handling and processing of ultrathin wafers utilizing existing and established equipment and facility lines. Using a single platform for bonding, debonding, and subsequent wafer cleaning with specialized adhesive as a first consumable and cleaning solvent as a second consumable allows this technology to be implemented while keeping deployment of resources and COO per processed wafer at a minimum.
Thus, temporary bonding/debonding offers an efficient, low-cost solution for providing the support essential to the creation of TSVs on ultrathin wafers. TSVs are increasingly proving critical to enabling achievement of the challenging interconnect and packaging requirements set forth by the International Technology Roadmap for Semiconductors (ITRS). The new process described above represents a high-yield, high-performance solution for simultaneously debonding and cleaning sub-100-micron thinned wafers up to 300mm in diameter, creating the support required by semiconductor manufacturers as they continually strive to adopt 3D packaging processes that take advantage of existing equipment and manufacturing infrastructures.
Acknowledgment
WaferBOND HT is a trademark of Brewer Science Inc.
Stefan Pargfrieder earned his degree in tech. physics at the U. of Linz, Austria, and did his master’s thesis in collaboration with Infineon Technologies. He is business development manager with EV Group, DI Erich Thallner Strasse 1 A-4782 St. Florian, Austria, ph +43 7712 5311 0; e-mail [email protected].
Bioh Kim received his bachelor’s and master’s degrees in materials science and engineering from Seoul National U. He is the director of business development for EV Group’s 3D and WLP efforts.
Jim Lamb received his chem. engrg. degree from U. of Missouri-Rolla and is director of corp. business development for Brewer Science; 2401 Brewer Dr., Rolla, MO USA; ph 573/364-0300; e-mail [email protected].