Issue

Key building blocks for a 22nm transistor

06/01/2008

Serge Biesemans, PhD,
department director, CMOS Device and Technology Research, IMEC

Understanding what a 22nm transistor will look like requires answers to many diverse factors. As a start, high–k/metal–gate stacks in a planar CMOS architecture, additive strain in the transistor’s channel, and abrupt junctions in combination with laser–only anneals and defect–free implantation are likely to constitute the transistor of the future.

I expect that the microelectronics community will find solutions to the challenges posed by the pathway to 22nm. For example, although laser anneals are very suitable for diffusion–less annealing and dopant activation, they are not the right tool for defect annealing. Therefore, we are now looking into the possibility of avoiding defect formation, e.g., by high–temperature implantation of dopants, or by implanting larger clusters of atoms such as decaborane (B₁₀H₁₄) or large molecule clusters instead of the conventional implantation of single dopant atoms.

However, thunderclouds may loom on the horizon as the industry pushes ahead. The possibility exists that in such architectures, abrupt junctions, high–channel doping levels (needed to control short–channel effects), and the persistence of residual defects eventually give rise to too much parasitic leakage and variability. In that case, I see a move toward multi–gate architectures (FinFET or MuGFET) as a feasible alternative. To electrically control the transistor’s channel, FinFETs and MuGFETs exploit the so–called double–gate effect instead of traditional channel doping and abrupt junction formation. Therefore, they are expected to have less severe intrinsic limitations.

Tremendous progress has been made in FinFET technology development, although problems related to 3D gate patterning and metrology remain to be solved. However, the latest evolution in DRAM scaling appears to be a valuable contribution to the maturing of these issues. Since the 70nm generation, recessed channel architecture transistors (RCATs) are being used in DRAM stand–alone products. An RCAT can be considered an inverse FinFET, using trenches instead of fins. Since this concept is soon running into scaling limits, the DRAM community is now considering the possibility of moving toward bulk–FinFETs. Of course, a DRAM cell transistor has a set of requirements that is somewhat different from our logic transistor, putting emphasis on density and off–state currents instead of on performance.

Yet, for a dense DRAM bulk–FinFET, issues such as gate patterning, metrology, junction technology, and equipment are to be developed as well, and logic FinFET technology can eventually fall back on their progress. Actually, it will not be the first time that DRAM acts as a trendsetter by introducing new materials or architectures before logic makes the move.

Eventually, the SRAM part of the logic chip can make a profit by implementing a FinFET architecture. By exploiting the double–gate effect and improving variability effects, the use of FinFETs has a positive effect on SRAM stability, which is a major challenge for further scaling. Just consider the fabrication of today’s multi–100 megabit 6T–SRAMs in a 6–sigma design. That’s a billion transistors with a too narrow distribution of threshold voltages. FinFETs have an advantage here, provided that extrinsic limitations such as line–edge roughness and gate profiles can be optimized. On the patterning side of dense SRAM or DRAM, the development of EUV lithography has made good progress very recently and demonstrated contact patterning using single exposures (as opposed to immersion 193nm that requires double–patterning techniques). If we can maintain the momentum, I am hopeful that EUV lithography will be employed at 22nm.

With these key building blocks and with a tremendous effort from the entire microelectronics community, the critical technical hurdles can be overcome and a scaled–down version of the 45nm and 32nm transistor???be it in a planar or a FinFET architecture???comes within reach. Whether these solutions will still be economically feasible is another fundamental question that deserves just as much attention.

Contact Serge Biesemans at IMEC, Kapeldreef 75, B–3001, Leuven, Belgium; ph +32 16 281 880; e–mail [email protected].