Instrumented wafers enable etch chamber matching
06/01/2008
This study describes Qimonda’s use of autonomous instrumented temperature and voltage sensing wafers for determining the causes of chamber mismatch in production plasma etch systems. Our testing showed clear relationships among etch chamber operating parameters, including a significant correlation between mean surface voltage (VRF) and CD and a reasonable correlation between temperature and etch rate and CD for most chambers.
The reactions of greatest relevance to plasma etch patterning take place at the surface of the wafer. Chemical reactions are strongly driven by wafer surface temperature. Physical reactions are driven by neutral flux, ion flux, and ion energy at the surface of the wafer. However, these conditions at the wafer surface are typically monitored indirectly.
Wafer temperature is primarily monitored by chuck coolant temperature and backside helium pressure. Ion flux and ion energy are estimated from voltage and current measurements in the external RF power delivery system. In most cases, no information is available about the actual wafer surface temperature, or about the current and voltage as they appear at the wafer surface.
 Figure 1. One week of production inline CD from nominally identical chambers. |
A chamber matching case is shown in Fig. 1, showing one week’s inline production CD data from six nominally identical chambers. By every existing metric???tool data, monitoring test wafer, and inline SEM CD???these chambers are in spec. At this 80nm process node (~100nm densely spaced line CD, ~150nm isolated line CD), these chambers show acceptable matching; however, for smaller geometries, CD variation of this magnitude across chambers is no longer acceptable. The purpose of this study was to see if instrumented wafers could help us understand the nature and root causes of the mismatch between chambers.
Methodology
The study began with off–the–shelf Integral SensorWafers [1], which measure surface temperature using 62 temperature–sensing ICs built into grooves milled into a standard silicon wafer. The grooves and sensors are then covered with a thinned (380μm) silicon wafer. The net effect is that the plasma “sees” a bare silicon wafer surface. As the thermal measurement delay through the silicon cover is ~40ms, for the purposes of this study, the temperature readings are assumed to be reasonably close to instantaneous surface readings. Surface voltage was measured with a PlasmaVolt SensorWafer. This measurement (called “VRF”) is that of a voltage drop across a surface–mounted capacitor; hence, it is proportional to the RF current through the wafer, at each sensor location.
Six production dielectric plasma etch chambers were evaluated in this study [2]. These chambers were nominally identical 300mm, multi–frequency RF, capacitively coupled chambers. Individual chambers on two cluster tools “03” and “09” are identified by letters A through D
(e.g., chamber 03D). All chambers were in normal mass production status at the time of measurement, having passed various qualification tests and demonstrating acceptable statistical process control behavior. Each chamber was “warmed up” using conditioning wafers prior to every instrumented wafer test and a waferless plasma clean was run immediately after each test.
Data was collected by running the instrumented wafers through standard etch production processes and a single–recipe DOE. The etch process recipes used were identical to those for mass production with one exception: Plasma optical emission feedback control (endpoint) automatically stops certain steps in both recipes, but since endpoint control could not be used for these tests, these steps were set to times typical for production.
The DOE was constructed as a three–factor, two–level series for a fluorocarbon etch process (FC DOE) similar to those used for both bottom anti–reflective coating (BARC) etch and the dielectric main etch, by varying pressure (+60% to –30% of nominal) and RF powers at 2MHz (??–33%) and 13MHz (??50%). A similar DOE was constructed for the carbon layer etch (CHM DOE) where pressure (+33% to –17%) and RF Power at 13 (??33%) and 60MHz (??50%) were varied.
At a 1Hz sampling rate, the instrumented wafers can collect 15–25 min. of data, depending on the number of sensors activated. Thus, to make the best use of tool time, tool process “recipes” were created that contained all the systematic variation of process variables combined into a single 11–step recipe. Both DOE experiments were planned to minimize and detect interactions between recipe steps by both randomizing their order and including multiple “centerpoint” (nominal settings) runs at the beginning, middle, and end of each recipe.
Temperature data collection was triggered automatically at a temperature of 35??C that occurred briefly after wafer placement on the ~ 45?? chuck. During transfer between chambers the sensor wafer temperature falls below the electrostatic chuck (ESC) temperature, preventing “memory” effects from previous measurements. Surface voltage data collection was started to coincide with the approximate plasma ignition.
Test wafer and inline data
Product CD was measured using an inline SEM with automatic pattern recognition measurement. The CD of each structure was an average of multiple linewidth measurements of the same line. Minimum space lines (here referred to as “DENSE”) and those with larger separation (here referred to as “isolated” or “ISO”) were measured to track results in each of these micro–environments. Standard mass–production measurements included dense and isolated line measurements at seven sites across the wafer surface, although 27 sites were measured in special cases where indicated. Sites were chosen from the same location within the lithographic exposure field to exclude some sources of lithographic non–uniformity.
Within 24 hours of the measurements, etch rate (ER) data was collected for chambers 03A, 03B, and 03D. The main etch (ME) rate was measured for silicon nitride removal, while the BARC etch rate measured i–line resist removal. ERs were measured using pre–measured blanket silicon nitride and photoresist films. Immediately before ER measurement, three “warm–up” wafers coated with photoresist were processed using the ER recipe/plasma clean to ensure consistent results.
Temperature correlations to etch rate and CD
A representative temperature data trace from a production recipe is shown in Fig. 2a. The various film layer etching steps can be seen clearly. The temperature values used for the correlation are those at the point of maximum temperature (Tmax) for a given step, BARC or ME. To provide a more accurate correlation to etch rate and CD, an interpolated temperature surface map was created. ER (49 points/wafer) and CD values (27 points/wafer) from their respective locations were correlated to the corresponding spatial location on the 62–sensor interpolated temperature map. Spatial correlation to VRF was not performed due to the limited across–wafer sampling with the VRF sensors.
ME and BARC etch showed a reasonable correlation (R2~0.7) to temperature for most chambers, as in the example for chamber 03D shown in Fig. 2b. The temperature correlations were similar for ISO CD (Fig. 2c). These results appear to make physical sense in that higher temperatures logically produce higher etch rates. Higher etch rates, in turn, make for smaller CD values. It is important to note that even with a fit of 0.7, there still remains 30% of the across–wafer variation that was not accounted for by wafer surface temperature alone.
DOE results
A representative temperature data trace (chambers 03A and 03B) for the DOE is shown in Fig. 3a. It is apparent that steady–state temperature was not achieved for most process conditions, and there was an overall warming trend during the recipe. The response of temperature to DOE parameter variations of pressure and RF power was markedly similar for all chambers in this study. However, the mean temperature response across the wafer at Tmax showed significant variation by chamber (Fig. 3b).
 Figure 3. DOE temperature response: a) representative Integral temperature response to DOE; b) DOE mean (Tavg across–wafer) temperature response, sorted by chamber. |
One significant discovery in this analysis was that the mean temperatures across these six chambers were grouped around the three shared chiller units. Chambers are paired by chiller units: 03A and 03C, chambers 09C and 09D, and chambers 03B and 03D shared the same chillers. (Data for 03D is not shown since priorities in production scheduling did not allow access to this chamber during this time period.)
The VRF data trace for the DOE (Fig. 4a) shows a ~2s ignition spike for each step, falling rapidly to a steady state value. Possible variations among ignition spikes were not analyzed in this study; instead, the across–wafer mean VRF response is read from the steady–state values for each step. An empirical regression model of the VRF response to the DOE variables was determined. As expected, VRF increased linearly with increasing RF 13 and RF 60 power. Both the mean VRF values, as well as the rate of increase (slope), varied by chamber. The response to pressure in this regime was insignificant. Further analysis revealed a significant correlation (R2=0.92) between mean VRF by chamber and the ISO CD data by chamber that is displayed in Fig. 1.
 Figure 4. DOE VRF response: a) PlasmaVolt VRF data collection for DOE recipes; b) implementation of VRF models to control CD. |
Combining the empirical models for VRF to RF power and VRF to ISO CD allowed a model to be constructed correlating RF power to ISO CD. This model indicated that product CDs could be matched by adjusting the RF powers in such a way as to make VRF match across chambers. Such instrumented wafer feedback and modeling could potentially be used to match complex process results across chambers through relatively minor tuning of process variables. In this case, changes to RF power to bring the chambers into match are predicted to be on the order of a few percent. A schematic representation for a production implementation of this model is shown in Fig. 4b.
Chiller coolant correction
During the evaluation period of the instrumented wafers, we discovered that the coolant composition in the 03B,D chiller was out of specification, and we were able to collect sensor wafer data before and after the coolant was changed. The recommended ESC coolant is a 50/50 (% volume) ethylene glycol/water solution. Refractometry data showed the coolant composition in the 03B,D chiller was 70/30 during our “before” measurements, and 50/50 “after.” The improved thermal conductivity of the 50/50 mix notably reduced the process temperature variation across the wafer, which resulted in a reduction of the average CD range across the wafer. The data shown in the table has a statistical sample size of 195 wafers.
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Reducing chamber mismatch
The following corrective actions are under consideration or are in some phase of implementation:
Chiller temperature mismatch: Use instrumented wafers to calibrate chiller temperatures.
CD mismatch among chambers: Explore the possibility of chamber matching through adjusting RF to match VRF readings.
Regarding thermal vs. physical contributions to etching mismatch: We plan to further investigate temperature vs. VRF responses to look for root causes. (In the case where the temperature to CR correlation is R2=0.7, it would be useful to determine the cause of variation for the other 30%. Experiments are underway on more fundamental etch processes, with the intent to examine chemical/physical contributions to plasma etch.)
Conclusion
Several relationships among etch chamber operating parameters were revealed during the evaluation using instrumented wafers. First, it showed a significant correlation between mean surface voltage (VRF) and CD. Creating a model based on the data indicated that CD could be matched between chambers by adjusting the RF powers to match VRF readings. This modeling could potentially be used to match complex process results across chambers through relatively minor tuning of process variables.
Temperature relationships were more challenging to understand: Several etch types showed a reasonable correlation between temperature, etch rate, and CD for most chambers???higher temperatures logically produce higher etch rates and higher etch rates, in turn, make for smaller CD values. But a significant amount of across–wafer variation was not accounted for by wafer surface temperature alone.
One production–relevant result from the instrumented wafer testing was the discovery, due to detected temperature variations, that the coolant composition in one dual–chamber chiller was out of specification. After the ESC coolant was restored, the improved thermal conductivity of the solution notably reduced temperature variation across the wafer.
Acknowledgments
Integral and PlasmaVolt, when used with the word SensorWafers, are trademarks of KLA–Tencor.
References
- P. MacDonald, G. Roche, M. Wiltse, “Yield Management Solutions.” Issue 2, 14 (2007).
- M. Tesauro, R. Koepe, T, Remus, G. Roche, and P. MacDonald, “Plasma Process Development and Control with Real–Time Critical Process Parameter Detection at the Wafer Surface,” AVS Symposium #54, Seattle, WA, October 2007.
- M. Tesauro, R. Koepe, T, Remus, G. Roche, and P. MacDonald, “Plasma Process Development and Control with Real–Time Critical Process Parameter Detection at the Wafer Surface,” GMM Workshop 2007, November 2007, www.iisb.fraunhofer.de/nutzergruppe–abscheidung–aetzen/programm_ws_nov_8_2007.pdf.
Mark Tesauro is a staff engineer/R&D project manager at Qimonda Dresden GmbH & Co. OHG Dresden, Germany; ph 49 351 4388 3103; e–mail [email protected].
Gregory Roche is a senior member of the technical staff at KLA–Tencor, Santa Clara, CA USA; ph 408/986 5642; e–mail gregory.roche@kla–tencor.com.