Etching new IC materials at 32nm and 22nm
05/01/2008
Silicon Valley was once the center of the silicon-based IC manufacturing world, and although IC fabs are now located globally, the valley maintains momentum as the center of IC R&D. The Northern California Chapter of the American Vacuum Society still runs regular users groups on important industry topics. In addition, the plasma-etch users group (PEUG) meeting on March 13 featured presentations by IBM and Applied Materials on advanced etch processes for 32nm and 22nm node ICs.
Nicolas Gani of Applied Materials’ silicon etch division presented on work done in collaboration with IBM on plasma etching for gate-stacks for 45nm and 32nm node CMOS transistors. Since the stack comprises multiple materials, different single-wafer etch chambers for different etch conditions are ideally clustered together into a single tool. One chamber is designed for polysilicon etching at relatively low temperature, while another chamber is designed for high-k/metal gate (HK+MG) material removal at relatively higher temperatures of 130??C-220??C.
High-k materials such as HfO2 demonstrate etch rates in Cl2 plasmas with zero bias power that increase linearly by ~4?? over the 100??C-200??C range, though rate studies indicate there is some ionization component to the etch even without bias. High source power can actually induce polymerization which shuts down the HfO2 etching. Using 20W bias allows for a 100s Å/min etch rate. One of the key issues in tuning etch processes is the elimination of any &ldqou;foot” at the bottom cross section of line-stacks. Applied Materials has shown that etching at >200??C leaves <1nm of a foot, while a 3-4nm foot is seen at <100??C. The temperature control is modest since for etching at >~150??C the reaction is surface limited so that uniformity across the wafer is guaranteed even with an ESC only controlling to ~5??C.
Nicolas Fuller of IBM Research talked about plasma etching challenges for 22nm node etching, with most of the work done at the company’s facilities in Yorktown Heights, NY, although unit process work was also done at East Fishkill and Albany. Device options for 22nm include finFETs and SOI, and both structures create unique etch challenges. &ldqou;The fin itself can charge,” explained Fuller. &ldqou;It may have a hardmask, and charging during the etch can produce an ion steering effect that induces greater etch rate in the middle of structures.” Going to 3D represents a challenge and an opportunity. &ldqou;Here, charging potentially represents an advantage. You might want to charge the metal gate to induce ion steering to minimize footing,” claims Fuller.
As complex as today’s leading-edge 45nm production may be, halving the scale seems like it could be an order of magnitude more difficult. For sidewall image transfer to get the types of structures at 22nm node fin pitches we may need some manner of atomic-level etching to conceptually match ALD. New line-edge roughness (LER) and linewidth roughness (LWR) issues will be induced by multiple exposures and multiple etches anticipated in 22nm integrated double-patterning process flows.
IBM showed that after lithography to form 24nm-wide lines at 80nm pitch there was 2.6/4.9 LER/LWR (3σ); and best lab results of 1.4/2.3 were achieved with multistage etches of organic/inorganic materials as masks using boutique combinations of e-beam and optical litho. Plasma etch work ongoing at Albany now suggests that high-frequency plasma parameters are the main factors that must be controlled to minimize LER/LWR. There’s barely any CD error budget left, and etch has to share the vanishingly few nanometers with lithography and metrology and deposition. Hold tight. –E.K.
Double development offers simpler double patterning
It’s convenient to visualize the image created by a photomask as a binary array of bright and dark regions. Yet in the era of subwavelength lithography, scattering around mask features actually creates a grayscale image. Intensity at the center of a bright area is near maximum, and intensity at the center of a dark area is near zero, but the areas in between are likely to have a smoothly varying intensity profile, with Gaussian distributions replacing sharp-edged delta functions. As a result, resist contrast defines the features actually transferred to the wafer. Above a given exposure threshold, photoacids in positive tone resist remove protection molecules, rendering the resist soluble in developer. The cleared, &ldqou;bright” areas of the resist pattern are those in which exposure intensity exceeds this threshold.
Lithographers use a variety of mask enhancement features to control optical scattering and maximize image resolution. Generally speaking, though, bright areas of the mask tend to become wider due to diffraction effects, while dark areas tend to become narrower. Attempts to compensate for this behavior tend to reduce the contrast between light and dark areas, and thus the available dose margin.
When positive imaging is used to print narrow trenches, most of the mask area is dark, while the trenches appear as bright lines. Diffraction at the edges of the trench regions tends to degrade the resolution of these features. In negative imaging of narrow trenches, on the other hand, most of the mask area is bright, improving contrast at the edges of the dark trench regions.
Traditionally, Shinji Tarutani and other researchers at Fujifilm Electronic Materials Research Laboratories explained in a presentation at the recent SPIE Advanced Lithography Meeting that achieving high resolution with negative imaging has been difficult. To achieve a high dissolution rate in an alkaline developer, negative tone resists incorporate polar and hydrophilic groups. Yet the cross-linking reaction that captures the exposed image may not destroy these groups. Rather, their presence can allow developer to penetrate the resist film, leading to pattern swelling, bridging, and other defects [1].
Instead, Tarutani explained, the Fujifilm group focused on negative development of conventional positive-tone resist. They found that an appropriate organic solvent can attack the acid-labile groups found in unexposed areas of positive tone resist. Under these conditions, the contrast in dissolution rates between exposed and under-exposed regions depends on the molecular weight and structure of the resist. Increasing the molecular weight slows the penetration of organic solvent, reducing the dissolution rate. By using a bright mask with negative developer, the group achieved linewidth roughness (LWR) of 4.2nm in 32nm trenches (128nm pitch). Positive developer was unable to resolve these features (see Fig. 1).
Though high-resolution patterning of narrow trenches is helpful, the ability to use both negative and positive development for the same resist raises even more interesting possibilities. If negative development clears the &ldqou;dark” areas of the areal image, while positive development clears the &ldqou;bright” areas, then what about the gray regions in between?
As the Fujifilm group showed, it is possible to tune the resist imaging threshold so that some regions lie below the exposure threshold for positive development, but above the threshold for negative development. These gray areas remain intact after both positive and negative development. As shown in Fig. 2, such regions occur at one-half the photomask pitch, placing an untouched resist column on either side of each mask feature. The effect is to double the pitch frequency, and thus the density of lines and spaces.
Double patterning is often proposed as a way to improve resolution without investing in more expensive exposure tools or more complex photomasks. For example, one proposed pitch frequency doubling scheme places a spacer on either side of a patterned hard mask. When the hard mask is etched away, the remaining spacer captures the desired pattern.
The key challenge for most double-patterning approaches is cost. The spacer-based approach adds additional deposition and etch steps. Other schemes can achieve a wider variety of patterns by using two different photomasks, but the additional exposure adds even more expense. From a cost perspective, Fujifilm’s use of double development looks very promising indeed.
So far, however, the work remains at the feasibility study stage. Initial results obtained 120nm pitch line and space patterns, using 0.75NA ArF dry exposure. Extrapolating this result to 1.35NA immersion exposure would give 33nm half-pitch resolution, but such fine patterns have not yet been printed. –K.D.
- Shinji Tarutani, Hideaki Tsubaki, and Shinichi Kanna, &ldqou;Development of materials and processes for double patterning toward 32nm node 193nm immersion lithography process,” Proc. SPIE, vol. 6923, paper no. 14 (2008; in press).
Freeze frame: JSR closes in on double patterning at 22nm
During the recent SPIE Advanced Lithography Conference, JSR Microelectronics reported on its development of a &ldqou;freezing material” for use in double exposure/double etch or double-exposure/single etch processes, achieving 32nm line and space patterns for 22nm node devices (see Fig. 1). The new material was evaluated on IMEC’s sub-32nm CMOS research platform, which is part of its advanced lithography industrial affiliation program. By using a material that freezes the first resist, it prevents the resist from either expanding or shrinking (i.e., CD growth), essentially cross-linking the resist. When the second resist layer is deposited, the two do not interact.
 Figure 1. Process flow of double patterning with resist &ldqou;freezing.” |
Mark Slezak, senior manager of lithography product development at JSR, told SST that the new material is ideal for brightfield applications (i.e., line first double-patterning [DP] processes), so logic and some memory applications should be a good fit (see Figs. 2 and 3). The freezing material is not as useful for darkfield applications, i.e., most memory applications that are trench first. However, he noted that the concept works well for shrinking trenches in a litho, etch, litho, etch DP application.
 Figure 2. Application example for a 32nm logic process. (Data courtesy IMEC) |
Slezak says the materials breakthrough had to meet two requirements: limiting the CD growth of the first resist pattern, and limiting the interaction between the second resist pattern and the &ldqou;frozen” first pattern. &ldqou;When we first came up with this process, we saw CD growth of about 10nm, which put a lot of pressure on that first lithography layer,” Slezak told SST. &ldqou;We’ve been able to minimize that growth to ~1-2nm, so now if the final goal is a 40nm line, we can image ~38nm and freeze it to a 40nm CD.”
 Figure 3. Application example for a 32nm memory process. (Data courtesy IMEC) |
The resists used to pattern both the first and second layers have the same solvent system, so to prevent the second resist’s solvent from washing away the first resist, the properties of the first resist have to be changed so that it becomes nonsoluble before the second can be applied, Slezak noted. &ldqou;To do that, the polymer must be cross-linked so the first resist is no longer sensitive to photons in addition to not being soluble in the second resist’s casting solvent. The cross-linking avoids re-exposure during the second patterning as well as interaction of the second resist’s solvent with the first resist’s solvent.”
&ldqou;By using a smart mask to decouple the two patterns that provide the final pattern, the freeze process is used to eliminate tight k1 lithography challenges,” according to Slezak.
&ldqou;In the case of a logic device, a logic pattern is broken up on the masks so the first patterning is done with mask #1 and the second pattern is done with mask #2, combining for a final pattern that eliminates the stress points (i.e., the low-k1 imaging points).” –D.V.
Turning an immersion litho ‘defect’ into a double-patterning ‘feature’
Immersion lithography introduced a new polarization problem because of contrast differences for the TE and TM modes of the exposure light. But a paper presented by Bruce Smith et al., of the Rochester Institute of Technology (RIT) at the recent SPIE Advanced Lithography conference suggested the intriguing possibility of turning this &ldqou;defect” into a &ldqou;feature” by using the effect to do double patterning with frequency doubling imaging. The technique might provide a single-exposure alternative to double exposure/double patterning schemes at future nodes.
While polarized light works fine with dry lithography, immersion litho has favored transverse electric (TE) polarized illumination for high-NA patterning, because the image modulation from the transverse magnetic (TM) component falls off rapidly at large angles. In fact, the RIT group finds, by using large oblique angles for imaging while controlling the resist/substrate reflectivity, TM polarization can be employed. Smith showed that by putting a highly reflective film under the resist and using TM illumination, the lines and spaces of an alternating line-space pattern were reversed compared to TE polarized light.
The RIT researchers suggested that it should be possible to use a multilayer resist stack (doing TE and TM imaging at different large angles) to perform a double exposure in one resist stack, rather than going to the double exposure/double patterning schemes now being devised for sub-45nm lithography. They devised a method for frequency doubling in a single exposure at large angles using the reflective component at the resist/substrate interface for their experiments. Maximum contrast was achieved at 45?? angles. Using conventional polyacrylate 193nm resist, the RIT group was able to achieve 20nm half-pitch pattern resolution with a 1.20NA, water immersion exposure tool, and they also showed results for 22nm half pitch at 1.05NA. A resist stack was used with light areas in one layer and dark areas in another layer. There were 30-40nm-thick regions in the resist, and the exposure was not too sensitive to thickness variations.
Smith explained that while the technique appears to work well for lines in two directions, it did not work so well for elbows. –B.H.