Fully gate-all-around silicon nanowire CMOS devices
05/01/2008
Executive OVERVIEW
Although CVD-grown nanowires are good for demonstration purposes, getting them into manufacturing calls for the utilization of CMOS fabrication methods. We present fully CMOS- compatible nanowire technology with applications and fabrication challenges. Gate-all-around (GAA) silicon nanowire FETs are demonstrated with excellent gate electrostatic control and near ideal turn-on behavior. The nanowire CMOS inverter logic operates down to VDD = 0.2V and is indicative of the potential of these devices for ultra-low power applications toward the end-of-silicon technology roadmap. Finally, we discuss the challenges specific to an advanced dielectric/electrode scheme in nanowire technology.
Since the late 1980s, the electronics industry has been dominated by the Si-CMOS (complementary metal oxide semiconductor) device with its growth guided by Moore’s Law. It has been possible mainly due to the scalable nature of the planar MOS (metal oxide semiconductor) transistor architecture and the monolithic integration of complementary devices, namely n- and pMOS, with tremendously large density and functionalities. Following the scaling, silicon integrated circuits (IC) technology based on planar CMOS has already entered an era where the transistor gate length has shrunk to <50nm in high-volume manufacturing. However, this planar device architecture is now gradually approaching the performance limit. For technology nodes in the sub-32nm regime (2013???2020) where the gate length of the transistor is projected to be <13nm, the International Technology Roadmap for Semiconductors (ITRS) [1] has highlighted several challenges.
The foremost issues are: 1) poor gate electrostatic control of the channel potential and thus degraded short-channel effects; 2) high gate leakage due to thin gate dielectric; 3) reduced channel mobility on account of increased doping in the channel; and 4) increased source/drain resistance. These issues cause higher off-state leakage and limit the drive current leading to compromised performance, defeating the main purpose of scaling.
 Figure 1. Progression of device structure from single-gated planar FET to fully gate all around (GAA) MOSFET. |
To continuously meet the scaling requirement, the industry is exploring combinations of new material variants (e.g., high-k dielectric replacing SiO2 as gate dielectric, metals replacing polysilicon as gate electrodes, and high mobility channels such as strained-Si, SiGe or Ge replacing Si) and novel device structures (e.g., nonplanar MOSFETs such as double-gate or tri-gated/Ω-gated FinFET, and ultimately, gate-all-around FET). Figure 1 depicts the progression of device structure from single-gated planar to fully gate-surrounded MOSFETs.
The increased number of gates enhances electrostatic control of the gate electrode over the charge carriers flowing from source to drain in the channel, and therefore reduces the parasitic short-channel effects. The GAA structure with the thin nanowire channel will provide the best gate electric field control as it has a virtually “infinite” number of gates with all the gates in close vicinity of the channel. Specifically, the GAA nanowire structure is considered a potential candidate to take CMOS electronics to the “end-of-the-silicon technology roadmap” by shrinking the gate length along with the nanowire diameter [2].
Fabrication of silicon nanowires
The ITRS [1] recognizes that the key challenges with one-dimensional nanowire channel structure are 1) realizing them with controllability and reproducibility, 2) positioning them in pre-defined locations and orientations, 3) forming contacts and interfaces with desired electronic properties and, most importantly, 4) leveraging them with existing Si-CMOS process infrastructure from the viewpoint of materials and tool sets. These challenges are perhaps raised from a perspective in which bottom-up techniques to grow carbon nanotubes (CNTs) and semiconductor nanowires are intensely used as the technologies to realize one-dimensional structures for CMOS. It is a daunting task for these techniques to mature and meet the stringent needs of the CMOS IC industry.
On the other hand, the above challenges can be overcome if nanowires can be formed using a top-down approach by taking advantage of the conventional CMOS process technologies and available infrastructures (and render these challenges a non-issue). We present such a top-down approach for fabrication of GAA nanowire devices.
The scientific basis of silicon nanowire formation in the approach we used is the well-known stress limited oxidation method [3], which occurs in silicon when it is geometrically constrained, as in the case of a fin-like structure. At low temperature, the oxidation of silicon is progressively slowed on the pattern corners due to increasing stress caused by the volume expansion, which inherently provides a large process window for achieving nanowires with controlled dimensions.
Our approach is fully compatible with the CMOS flow in both materials, and toolsets and technology. The approach is inherently devoid of issues faced by the bottom-up techniques such as placement of nanowires, and formation of reliable electrical contacts to the nanowire for source and drain electrodes. Using our method, nanowire GAA MOSFET channels, linear array channels, and large area networks, including arc shapes of nanowires, could all be formed (Fig. 2) with high yield by defining them in the mask, and following the same/similar process sequence.
We have demonstrated Si nanowires down to 3nm dia. with this top-down approach using standard wafer fabrication processes by appropriately sequencing the photolithography, etching, and oxidation steps [4]. After patterning the minimum possible dimension, the silicon fin structures on SOI wafers are subjected to stress-limited oxidation that results in silicon nanowires. Based upon the fin aspect ratio, this method results in either one or two nanowires per fin. The challenge in achieving the twin wires is control over the cross-sectional shape of the nanowires. We have obtained wires with triangular cross section as well.
GAA Si-nanowire FETs
Once the nanowires for the channels are formed, subsequent steps of gate dielectric/electrode growth/deposition, source/drain implants, and metallization similar to the conventional CMOS process are used to fabricate a GAA-FET, which is regarded as the ultimate transistor in terms of gate electrostatic control over the charge transport in the channel.
 Figure 3. ID-VG (transfer) at a) room temperature for NMOS and PMOS, and b) low temperatures for NMOS with channel length of 350nm. |
Figure 3 shows the transfer characteristics of GAA n- and pFETs with a channel length of 350nm. Almost DIBL free characteristics with near ideal subthreshold slope (SS) approaching the fundamental thermal limit of 60mV/dec set by thermal energy indicate the excellent electrostatic control achievable in these devices.
We have conducted detailed transistor transport investigation from room to low temperatures (~5K), which gives insight into the details of quantum mechanics in play at these finer dimensions. These measurements at low temperatures clearly bring out the sub-band splitting in the allowed energy bands and its impact on carrier transport through inter-sub-band scattering. At extremely low temperatures (<77K) and low drain voltages (~50mV), we observe wiggles in the variation of drain current with gate voltage, which is identified as a signature of sub-band splitting.
Further, contrary to expectations, the drain current decreases as the temperature decreases, indicating the presence of an additional scattering mechanism other than phonon, coulomb, and surface scattering. We infer this to be because of inter-sub-band scattering. This form of scattering becomes important due to large energy gaps (in excess of ~50milli-eV) between the sub-bands obtained for such low dimensions. Our devices therefore play the role in providing firsthand experimental results to enable the modeling of one-dimensional semiconductor channels and therefore are very valuable from a fundamental physics point of view. The major advantage of the top-down approach is that once the device development is demonstrated, integration of these devices in circuit functionality is rather straightforward. We integrated the GAA nanowire FETs into a CMOS inverter logic gate. Figure 4 shows typical layouts of integrated n-channel and p-channel nanowires to provide an inverter function. This demonstration involved use of different numbers of nanowire channels for n- and p-transistor to match their drive currents, taking care of the difference in mobility of electrons and holes.
The inverters show “best in class” performance in terms of sharp transitions, high noise margins, and low power dissipation among reported nanowire and carbon nanotube devices. This is the first circuit level demonstration using a CMOS-compatible top-down approach, and the results are better than those achieved using other techniques of integration of nanowires in CMOS functionality [5].
Interestingly, these inverters function well even at ultra-low operating voltage (VDD = 0.2V) as indicated by the input-output characteristics in the butterfly shape shown in Fig. 4c. The large noise margins are clearly seen with maximum values of NMH = 0.09V (45% of VDD) and NML = 0.06V (30% of VDD). The short circuit current in this inverter is as low as 6pA.
High-k dielectric/metal-gate electrode
As silicon technology scaling progresses, high-k dielectric and metal gate electrodes are poised to replace SiO2 as gate dielectric, and polysilicon as the gate electrode, respectively. We have observed that when a silicon nanowire is surrounded by a HfO2 high-k dielectric and TaN metal gate electrodes, large stress is imparted onto the Si nanowire to the extent that it is physically twisted. We observed that the nanowire could be elongated by as much as 3% without breaking as a result of this twist [6].
The causes of the buckling/twisting of nanowires in the present case appear to be the intrinsic mechanical stress in the metal layer???a characteristic property of the film???and the thermal stress due to mismatch in the expansion coefficients of the silicon nanowires and the gate metal. The localized heating of nanowires during metal deposition, as they are isolated from the silicon substrate, could be responsible for the thermal stress. At the nano-scale dimensions, the surface flaws are extremely small and therefore Si nanowire can bend without breaking. True to this expectation, the GAA-FET functions like a normal transistor with an excellent sub-threshold slope and a high Ion/Ioff ratio.
One implication of the twisted nanowire is that it can be viewed as a model structure for studying the nano-mechanical properties of silicon. Recently, it has been reported [7] that a silicon nanowire exhibits a large piezo-resistance compared to silicon in bulk form. This giant piezo-resistance effect in silicon nanowires may have significant implications in nanowire-based flexible electronics, as well as in nano-electro-mechanical systems (NEMS). A top-down technology can be easily exploited to realize smart piezo-resistance based high sensitivity pressure, motion, and position sensors; these are applications beyond conventional CMOS technology.
3D stacked SiGe nanowires
In further progress using silicon nanowire platform technology, we have demonstrated 3-dimensionally stacked SiGe nanowires and also demonstrated GAA-FETs using these stacked nanowires as channels [8]. Such architectures allow the saving of silicon real estate and the packing of more channels in a given footprint.
We use SiGe as the sacrificial layer in a stack of alternating Si and SiGe layers grown epitaxially for this purpose. Due to the faster oxidation rate of SiGe than Si, the SiGe layer gets fully consumed during oxidation. Ge from the oxide grown from the SiGe layers gets segregated in the Si layers. Thus, during the oxidation step, two events happen: 1) SiGe layers get oxidized and 2) Ge diffuses into adjacent Si layers, converting them into SiGe [9]. This dynamic process results in SiGe nanowires embedded in SiO2. The concentration of Ge is more on the surface than in the core of the nanowires. By etching away the SiO2 using wet chemistry, we obtain vertically stacked SiGe nanowire bridges.
The transfer and output characteristics of n- and pMOS devices, with 500nm channel length, fabricated on these stacked nanowires indicates that turn-on behavior and gate electrostatic control is as good as for the twin Si nanowire devices presented in the previous sections. Further, the gm-VG plots show a peaking behavior for pFET???suggesting quantum confinement of holes in the [Ge]-rich outer-surface of SiGe. This reasoning infers confinement of electrons in the core Si for nFETs, which is expected to significantly reduce the impact of gate field on electron mobility. We observed a nonpeaking behavior in the gm-VG for nFETs.
The output characteristics of these stacked channel devices show almost the same drive current for n- and pFETs due to high mobility of holes in SiGe channels and possibly further increase due to the compressive strain along the channel caused by Ge condensation effects. Alas, the drive current is found to increase proportionally to the number of stacked channels for nMOS and p-channel devices as expected.
Conclusion
We have demonstrated that GAA Si-nanowire FETs with nanowire channel diameter scaled down to 3nm can be realized using a fully CMOS-compatible top-down approach. This alternative route to nanowire electronics renders the issues related to placement of wires at desired locations, achieving nicely behaving source and drain junctions related to the bottom-up approach of grown nanowires, to insignificance. Thus the focus on how to grow, position and align, and communicate with the nanowires becomes almost redundant.
We have further realized CMOS inverter logic and 3D stacked SiGe nanowire GAA-FETs with excellent performance using our top-down approach. Functionality of nano-wire CMOS inverters at an ultra-low VDD value of 0.2V with excellent noise margins indicates the potential of these devices for ultra-low power applications.
We have observed quantum mechanical effects on the carrier transport in these devices, which is a unique characteristic of low-dimensionality. Severe twisting of the nanowire is observed in the case of an advanced metal gate stack.
The top-down CMOS compatible approach that was introduced can potentially address the needs of “end-of-the-silicon technology roadmap” and beyond the CMOS era. Other than mainstream CMOS IC applications, the interesting nanoelectronic and nano-mechanical properties of silicon nanowires would open up new application opportunities for silicon technology in the areas of chemical and bio-sensors, flexible electronics, and other smart NEMS (e.g., piezoelectric motion sensors).
References
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- J. Kedzierski et al., “Novel Method for Silicon Quantum Wire Transistor Fabrication,” J. Vac. Sci. Technol. B 17(6), Nov./Dec. 1999, pp. 3244-3247.
- N. Singh et al., “Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance,” IEDM-2006, pp. 547-550.
- D.W. Wang et al., “Complementary Symmetry Silicon Nanowire Logic: Power-Efficient Inverters with Gain,” Small (www.small-journal.com), Vol. 2, No. 10, 2006, pp. 1153-1158.
- N. Singh et al., “High-Performance Fully Depleted Silicon Nanowire (Diameter =5 nm) Gate-All-Around CMOS Devices,” IEEE Electron Device Letters, Vol 28, No. 7, July 2007, pp. 558-561.
- R. He et al., “Giant Piezoresistance Effect in Silicon Nanowires,” Nature Nanotechnology, Vol. 1, 2006, Oct. 2006, pp. 42-46.
- W.W. Fang et al., “Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors,” IEEE Electron Device Letters, Vol. 28, No. 3, pp. 211-213, 2007.
- P.-E Hellberg et al., “Oxidation of Silicon-Germanium Alloys: An Experimental Study,” JAP 82(11), 1997, pp. 5773-5778.
Navab Singh received his M.TECH. in solid state materials from IIT Delhi, New Delhi, India, and is a member of the technical staff at the Institute of Microelectronics, 11 Science Park Rd., Singapore Science Park II, Singapore, 117685; ph 65/6770-5710; e-mail [email protected].
Kavitha D. Buddharaju received her MS from Louisiana State U., Baton Rouge, LA, and is a research engineer at the Institute of Microelectronics.
Ajay Agarwal received his PhD from BITS Pilani, India, and is a member of the technical staff at the Institute of Microelectronics.
Subhash C. Rustagi received his MSc and PhD degrees from Kurukshetra U., Kurukshetra, Haryana, India, and is a member of the technical staff at the Institute of Microelectronics.
G. Q. Lo received his PhD from the U. of Texas at Austin, and is nanoelectronics and photonics program director at the Institute of Microelectronics.
Narayanan Balasubramanian received his PhD from IIT Madras, India, and is the semiconductor process technologies lab director at the Institute of Microelectronics.
Prof. Dim-Lee Kwong received his PhD from Rice U., Houston, TX, and is executive director at the Institute of Microelectronics.