Issue



System-in-package integration of passives using 3D through-silicon vias


05/01/2008







Executive OVERVIEW

Future generations of cellular RF transceivers require higher degrees of integration, preferably using the third dimension. System-in-Package (SiP) applications have been shown for integrated 3D “trench” capacitors in silicon with a new world record capacitance density of =400nF/mm?? and break-down voltage >6V using Atomic Layer Deposition (ALD) of multiple MIM layer stacks of high-k dielectrics (Al2O3) and conductive layers (TiN). Different techniques may be used for through-silicon via (TSV) drilling and filling to allow for 3D die and wafer stacking with a small form factor. Both dry and wet-chemical methods were applied successfully in both the drilling and filling. Photo-electrochemical etching yields ultrafine high aspect ratio (~1.5μm??200μm) vias. A new “bottom-up” Cu-electroplating method and some preliminary Cu-paste filling tests show options for via metal formation.

Highly integrated cellular RF transceiver modules are in full production at NXP Semiconductors using their silicon-based System-in-Package (SiP) technology [1]. This new technology uses back-end silicon processing to integrate passives onto a silicon substrate that can serve as a platform for the heterogeneous integration with active component dies, MEMS dies, etc. As an example, a transceiver IC can be flip-chip mounted onto this passive component silicon substrate, thus minimizing interconnect parasitics and footprint area. This sub-assembly is then flipped back into a standard IC-sized lead frame package.

The passive die is made in the so-called Passive Integration Connecting Substrate (PICS) technology developed to integrate passive components such as high-Q inductors, resistors, accurate MIM capacitors and, in particular, high-density (~25nF/mm2) MOS “trench” capacitors for RF-decoupling and filtering. These capacitors are fabricated in RIE-etched arrays of high aspect ratio macropores with ~1μm widths and spacing and up to ~30μm depths. Capacitors with ~30nm ONO (i.e., silicon Oxide/Nitride/Oxide) dielectric and a poly-Si/Al top electrode had superior performance, with ultra low-loss factors (ESL <40pH and ESR <150mΩ), a high dielectric breakdown voltage (Vbd ~30V), very low leakage (<1nA/mm2 @ 22V), and a long lifetime of 10 years at 10V intrinsic operating voltage [1]. This year second-generation high-density capacitors (80nF/mm2, Vbd ~15.5V) was qualified by NXP for production [2-3].

The major advantage of the Si-based RF-SiP technology is that it allows the integration of high-quality passive components using relatively low-cost silicon processing. In addition, it allows active components such as transistors to be fabricated for optimum performance in different process technologies (CMOS, Bi-CMOS, or GaAs) and connected with fine-pitch interconnect due to the zero or minimum mismatch in thermal expansion.

The next stepping stones anticipated toward increased capacitance densities (>400nF/mm2), functionality and miniaturization by SiP integration are the use of so-called high-k dielectrics (based on Al2O3, HfO2, etc.) and conductors like TiN to compose MIS and MIM “trench” capacitors [2,4,5]; and etching and Cu-filling of through-silicon via (TSV) holes, with typically 10-100μm diameters and depths of 30-300μm.


Figure 1. Different generations of silicon-based SiP modules using 3D die stacking and packaging.
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This concept enables true 3D die- and wafer-stacking and generic SIP integration with small form factors. Figure 1 illustrates the different SIP generations under development at NXP.

Capacitance enhancement techniques are known from CMOS technology. One emerging technique used here is Atomic Layer Deposition (ALD) to grow MIS or MIM layer stacks of so-called “high-k” layer dielectrics and conductive layers [2,4,5]. However, the application of ALD onto wafers with high aspect ratio trench and macropore topography leads to additional challenges: The roughness on the trench sidewalls may cause undesired lower breakdown voltages. Also, the formation of interfacial oxide layers may lead to undesired lower relative dielectric constants, and far lower capacitance density than expected.

Furthermore, good step coverage and micro-structure (morphology and texture) in pores are necessary to achieve good insulating layers and are certainly not obvious. In ALD, adsorption and desorption of the different precursor vapors play an important role in filling and emptying the pores. In particular at the given pressure (typically ~10mTorr) and macropore dimensions the ALD process proceeds in a different diffusion regime (Knudsen diffusion), limiting the free diffusion of the gaseous ALD reagents and products. It turns out that the ALD process window is different from ALD on flat substrates and needs adaptation to be applied in deep pores [6]. In the case of high aspect ratio pores, extended purge times are needed to ensure good-quality layers.

The growth by ALD (plasma-assisted and thermal) of high-k dielectric layers (Al2O3, HfO2, etc.) and conductive layers (TiN) on wafers with a large topography has been studied extensively. The results point to a growing perspective for ALD-grown MIS and MIM capacitors with ultrahigh capacitance density, especially when low-temperature growth (back-end of line temperatures =400??C) is possible.

We have shown earlier that Plasma-Assisted ALD of TiN using a combination of TiCl4 precursor dosing and remote H2-N2 plasma exposure has great potential for applications requiring low temperature (100-400??C) [7]. Thus TiN can be grown with good uniformity on top of a “classical” silicon oxide-nitride-oxide (ONO) dielectric layer.

The second example is on a triple MIM “trench” capacitor stack grown on an (arsenic) n++-doped silicon substrate. In this substrate, fields of macropore arrays were etched with ~1.5μm pore diameter, 30μm pore depth, smooth pore walls, and a rounded bottom [8,9]. Figure 2 shows the layer stack. Note that the first dielectric layer is a 5nm thermally grown SiO2 layer to avoid any complication due to possible formation of native oxide layers. Next, a stack of TiN/Al2O3/TiN/Al2O3/TiN was grown on top with an advanced Jusung Engineering Eureka ALD reactor to complete the triple MIM capacitor stack. The TiN layers were deposited at 400??C from TiCl4 and NH3 vapor dosing. The Al2O3 layers were grown at 380??C from trimethyl aluminum (TMA) and O3, thus avoiding the oxidation of the TiN electrode layers.

The precursor pulse/purge ratios of the Al2O3 and TiN deposition steps were optimized for maximum step coverage throughout the macropores. Part of the wafers were annealed in O3 (5 min. at 400??C) after each Al2O3 deposition step to improve the dielectric isolation and breakdown properties.

A dedicated mask set was used to enable the simultaneous formation of planar and trench capacitors and to allow the subsequent electrical testing of the individual capacitors as well as the total capacitor stack (Fig. 2b). After patterning of the contacts, the total structure was covered with a low-temperature scratch protection oxide. Finally, contact holes were opened and bond pads were formed. The TEM images in Figure 2c show the excellent step coverage of the entire multilayer stack across the 30μm pore depth.


Figure 2. Scheme of triple MIM multilayer stack a) composed of three TiN and three dielectric layers, b) in a test capacitor layout where the TiN electrode contacts C1-C3 are at the front side, and the substrate contact is at the back side, and c) High Angle Annular Dark Field TEM cross section with bright-field TEM insets of the triple MIM capacitor layer stack.
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Capacitance measurements performed at 10kHz showed a world record of 400nF/mm2 capacitance density, averaged over 35 trench capacitors with 100??100μm2 electrode surface. Electrical tests using I-V curves show improved leakage current levels upon O3 annealing after deposition, for both the planar and trench capacitors. Weibull-plots also indicate the benefit of the O3 anneal, yielding reproducibly low leakage and high breakdown voltage. More details on the electrical characterization have been published elsewhere [10].

TSV drilling and filling

One challenge in 3D integration is the multitude of technology options in manufacturing, each option having different cost implications [11]. Depending on the specific application, the different process steps need to be compatible with the pre- and post-processing. Options such as “vias formed in front-end process” or “vias formed in back-end process” determine the applicability of materials and processes.

Through-silicon via (TSV) technology requires the following basic process steps:

  • Via formation;
  • Via isolation;
  • Seeding and barrier coatings;
  • Via filling with conductive material; and
  • Redistribution and finishing.

There are wet and dry options, both for the etching of TSVs and for their subsequent filling with copper.

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Dry-etching. The most widely accepted way of via hole formation is by reactive-ion etching (RIE) [9], of which the patented Bosch-process is the most popular. Typically the vias are anisotropically etched by alternatively introducing SF6/O2sub> etching gas and C4F8 passivation gas into the plasma. Dry-etching yields limited aspect ratios (20-30) and it is a single-wafer process, yet highly flexible in choice of substrate doping type and level. Recent RIE options for deep silicon vias include the alternative cryogenic processing and high-density expanding thermal plasma source for high-speed etching [12].

Wet etching. Less known is a wet etching method, that has been successfully used to obtain macropore arrays for trench capacitors [8,13]. Here, the macropores (typically 1-10μm wide) are etched in (100) Si-wafers in two steps. First, a pattern of {111}-oriented micro-indentations is pre-etched using potassium hydroxide (KOH) or tetramethyl ammonium hydroxide (TMAH). Next, the deep vias are obtained by photo-electro-chemically etching the wafer in an aqueous HF solution. The anisotropic wet-etching is based on the creation of holes by wafer backside illumination. The holes travel to the micro-indentation regions at the wafer front side where they sustain the preferential anodic dissolution of Si by HF. By proper tuning of the light intensity the hole transport and the diffusion of F- ions in the liquid can be balanced.


Figure 3. SEM image of a wet-etched blind via hole array [8].
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Figure 3 shows that these pores can be easily wet-etched in lightly n--doped Si up to aspect ratios of 200 or more. Wet etching is also possible for lightly p--doped Si without irradiation of the wafer backside [13]. Finally, the multiple via array can best be Cu-filled by backside “dry-film” seeding and bottom-up Cu-plating. The wet via etch method suffers from the fact that one can only use limited substrate doping levels. The Table summarizes the pros and cons of dry and wet etching for TSV formation.

Characteristics of pore etching methods

Wet-filling. Figure 4 illustrates the process sequence that we developed to manufacture oxide-insulated vias with so-called bottom-up Cu electroplating for critical via conductivity criteria (e.g., RF applications). The method is aimed at BEOL (low-temperature) processing and based on the use of a sacrificial PMMA layer that is spin-coated over the wafer to temporarily cover the blind vias.


Figure 4. Schematic cross sections showing the process flow for bottom-up Cu growth in via holes; a-b) oxide mask deposition and opening, c-d) blind via etching and oxidation, e-f) polymethyl methacrylate (PMMA) spin coating and CMP, g) Cu-seed layer deposition, h) wafer backside thinning, i) PMMA removal, and j-k) bottom-up growth.
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After curing the PMMA and polishing it back to coplanarity, a 50nm thin Ti adhesion layer is deposited by sputtering, followed by ~1μm Cu seed layer deposition. Then, the wafer is thinned from the backside to open the vias. Next, the PMMA is removed by heating the wafer to 300??C in nitrogen, so that a thin seed layer membrane remains to cover vias with diameters 10-150μm.


Figure 5. a) SEM image of a 20μm-diameter via after “bottom-up” electroplating in a fountain-type bath using CuSO4 without organic additives, where arrows indicate growth interruption (after 1 and 2 hr) and stopping (after 3 hr), and b) X-ray topograph of bottom-up grown Cu-vias.
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Figure 5a shows a typical SEM image of “bottom-up” electroplated Cu in a 20μm-wide via. Figure 5b shows a typical X-ray topography image of such vias. The resistivity of this material was =3μΩ??cm. Characteristic for this method is that one needs no seeding inside the high aspect ratio via holes. The process should be continued further by applying isolation at the nonseeded side (e.g. BCB or polyimid) and subsequent patterning.

Dry-filling. One method of Cu-filling that we tried for noncritical via conductivity criteria is paste printing [15,16]. 150mm diameter Si-wafers were prepared by RIE to form arrays of medium size vias, with diameters 10-100mm. Type AE1650 composite Cu-paste supplied by Tatsuta (Japan) was used. This paste consists of silver-coated copper grains, with a size of 2-3 mm, embedded in an organic binder. Both blind via arrays in thick wafers and through-vias in wafers thinned down to 200μm were successfully filled by using a vacuum-assisted high paste printing pressure process. The resistivity of the bulk material was measured to be ~38μΩ??cm.


Figure 6. Top SEM view of 200μm deep ‘blind’ vias after paste printing, a) via =30μm, b) via =10μm.
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This paste shows excellent properties for filling vias with a high aspect ratio. Figure 6 shows plan-view SEM images of 10mm and 30μm-wide vias filled 200mm deep with this copper paste. The filling properties were confirmed by angular X-ray inspection and cross-section optical microscopy (Fig. 7).


Figure 7. Cross-section micrograph of through-vias with 80μm diameter filled with copper paste.
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After filling and curing (30 min. at 160??C) of the copper paste, a preliminary electrical evaluation was done by measuring with a four-point probe. These measurements showed that the resistivity of this material inside the pores was around 135μΩ??cm. This value is indicative for nonoptimum current percolation caused by the limited contact between the particles and by the existence of voids inside the filled vias. It can also be ascribed to a high contact resistance between the paste and the distribution layer. Yet, it can certainly be further optimized (e.g., by using low-melting-point nanoparticles, better curing, etc.) and shows that paste printing may soon be a potential low-cost alternative for less-critical via interconnect applications. Further analysis on chain structures of these vias is ongoing.

Conclusions

We have investigated a few technology options in 3D passive integration as well as in through-silicon via (TSV) technology. In passive integration we made Si-integrated “trench” capacitors composed of triple MIM layer stacks. Optimized ALD processing in 3D silicon and post-deposition annealing in O3 gave world record capacitance densities up to 400nF/mm2, breakdown voltage >6V and low leakage current (~10nA/mm2 at 3V).

In TSV technology we have shown that very fine and high aspect ratio (~1.5μm ?? 200μm) via arrays can be wet-etched, as an alternative to the conventional RIE etching. Finally we report on via Cu-filling by a “bottom-up” electroplating method and on preliminary copper paste filling experiments that could offer a low-cost alternative for non-critical applications.

Acknowledgments

Included as co-authors are K.B. Jinesh from NXP Semiconductors Research, M. Burghoorn, F. Sanders, and T. Sakai from Philips Applied Technologies, M.A. Verheijen, R. Weemaes, and M. Kaiser from Philips Research, D. Blin from Jusung Engineering Europe, and S.B.S. Heil, M.C.M. van de Sanden, and W.M.M. Kessels from the Eindhoven University of Technology. Part of this work is funded by Senter-Novem, The Netherlands (Project ‘INNOVia’, IS044041). The collaboration with Mrs. N. Fujita at Sanyu-Rec (Japan) on Cu-paste printing and with our colleagues at NXP in Caen, France, on the RF-SiP modules is gratefully acknowledged. PICS is a trademark of NXP Semiconductors. Eureka is a trademark of Jusung Engineering.

References

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Fred Roozeboom is a Fellow in a team working on passive and heterogeneous integration at NXP Semiconductors (formerly Philips) Research in Eindhoven (Netherlands) and also part-time professor at Eindhoven U. of Technology. He leads a team on passive and heterogeneous integration. NXP-TSMC Research Center, High Tech Campus 4, mailbox WAG02, 5656 AE Eindhoven, The Netherlands; ph +31-40-2728608; e-mail: [email protected].

Johan Klootwijk is a senior scientist at Philips Research (Eindhoven, Netherlands), since 1997, where he is responsible for technology and test structure development, in particular bio-nanosensors and 3D integrated batteries.

Wouter Dekkers has been a technologist with NXP Semiconductors Research, working on passive and heterogeneous integration. Since 2007, he has been involved in related technologies for lighting applications at Philips Research.

Yann Lamy joined NXP Semiconductors in 2006 as a research scientist on passive and heterogeneous integration after he received his PhD from the U. of Limoges, France, on work in magnetic thin films at CEA-LETI.

Eric van Grunsven joined Philips Applied Technologies in Eindhoven, The Netherlands, in 1989. He is a senior project leader in charge of various projects in Electronic Packaging and Thin Films.

Heondo Kim is ALD director at JUSUNG Engineering Co. Ltd. in Gyunggi-Do, Korea, which is one of the world’s leading equipment suppliers for semiconductor, flat panel, and solar cell applications.