Technology News
04/01/2008
Double patterning will challenge litho, metrology, computation
While 193nm immersion lithography has taken the industry to 45nm, it will get progressively tougher to move below that. Lithographers will struggle with shrinking margins, more metrology and process control, along with extensive computation, plus double exposure for critical layers, which multiplies their problems.
The SPIE Advanced Lithography Conference in San Jose, CA (Feb. 24-29) explored this road ahead. Below 40nm, lithography becomes much more sensitive to stepper variation, and computational optimization will be required, according to Martin van den Brink, EVP, ASML, in a plenary talk. Lithography uniformity becomes critical, and metrology will be very difficult, especially with double exposure.
“Stepper controls are not well used today,” he said. It is possible to adjust dose point-by-point across the wafer, he suggested, but only with a tremendous amount of computation. Angle-resolved scatterometry feedback loops in production with a DoseMapper recipe might provide optimization. There also must be increased feedback from manufacturing to design, van den Brink added.
While EUVL continues on track for 22nm, he believes that memory makers will make strong use of double-patterning before going to EUV. Overlay and CD control using application-specific scanner tuning with fast, integrated metrology feedback will help make this possible, according to van den Brink. The process will also require pattern-split software.
D. Mark Duncan, president/CEO of Micron, agreed in his plenary talk that double patterning will be needed for future memory cells, but as the shrink continues, he foresees accelerating patterning costs. Going to 3D will forestall the move below 32nm for a time, he suggested.
Pushing NA higher for immersion lithography using new lens materials and a higher index-of-refraction fluid, could help reduce the challenge. But this will not be an option for 22nm, pointed out Toshikaya Umatata, GM of development headquarters for Nikon Precision, in a presentation a day earlier.
“High index does not match with the [ITRS] Roadmap,” he stated. Instead, at 22nm, EUVL will be the only candidate for general patterning, he added.
Micron’s Duncan did an analysis that supported this view. “I am confident that EUV is at the end of the Roadmap,” he stated. He sees EUV as the route to lowering rising patterning costs in the 2010-2012 timeframe. Duncan pointed out that chipmakers have to make massive bets on new factories, spending $3B on a new fab, much more than for an auto assembly plant, for example. Only an offshore rig, at $1.5-$2B, comes close. Yet, Duncan showed that the incremental gain in dollars/die would be shrinking significantly over the next few nodes.
ASML’s van den Brink took note of this investment concern in discussing the push toward higher productivity exposure tools. An analysis shows that acceleration is much more critical than scan speed, he explained. Right now, he said, an immersion tool can move at 600mm/sec, but to boost productivity further, the goal is to push that beyond 1m/sec, with lower defects and even tighter metrology overlay capability, moving from 4nm down to 2nm. Current 193nm immersion tools reach an NA of 1.35 without new lens materials and higher-index fluids, which is scalable down to 38nm, he said. Then double patterning, and eventually EUVL, will be needed.
While some experimental EUV tools are in operation, the technology will not be suited for volume production until an entire infrastructure is in place, pointed out Ben Eynon, associate director of SEMATECH’s lithography division in Albany, NY (assigned from Samsung). He reviewed the EUV infrastructure status at a pre-conference session organized by KLA-Tencor.
A major concern is an X-ray source that can deliver sufficient power to the wafer to meet reasonable throughput goals. Current sources can deliver 6W to an intermediate focus point, but 180W will be needed. “We need two orders of magnitude improvement, and that is a big challenge,” he said.
One source candidate is a discharge-produced plasma (DPP), but this involves a heavy heat load and does not scale well. More promising, according to Eynon, is a laser-produced plasma (LPP), using droplets of tin. The burst power needs to be focused, but the scalability is promising, he said.
EUVL will also require a resist that provides high resolution, allows adequate throughput, and minimizes line-edge roughness (LER). Right now, candidate resists that meet one requirement fail at the others, so improved materials will be needed to meet all three together.
Reflective reticles are essentially mirrors that must be flawless, Eynon explained. Any flaw on the glass substrate is greatly amplified after depositing 80 alternate layers of silicon and molybdenum over a 10hr period–any pit or particle would build up, making the reticle useless. Methods are being developed to remove any particles over 4nm high, and each layer may be smoothed out as deposition proceeds to minimize potential flaws. The eventual target is about one defect every five blanks or so, Eynon said.
For production, an EUV aerial imaging tool will be needed, he said, but the market will be so small that Sematech will need to help in the development.
“EUV still looks more cost-effective than double exposure, if we can develop it in a reasonable time,” Eynon explained. “That’s why we’re still pushing.” –B.H.
Tela Innovations lays it all out straight
Getting the most function out of the least chip area has been the main goal of IC designers since the beginning of the industry. Their creativity gave rise to complex 2D layouts that were shrunk geometrically one generation after another until about the 90nm node. At that point, the fact that the circuit features had become so much smaller than the exposure wavelength made imaging problematic. Circuit variability increased and lithography hotspots appeared at corners, isolated contacts and other structures, limiting yield. Attempts to restrict designer creativity to manufacturable shapes through restrictive design rules had only limited success.
Now, Campbell, CA-based startup Tela Innovations proposes a radical step to solve the industry’s layout problems by employing only certain pre-defined linear topologies. Previous proposals to limit design flexibility in that way had been rejected because of the fear of increased circuit area and the cost of redesigning entire cell libraries. According to Neal Carney, Tela VP of marketing, those problems have now been overcome as the result of three years’ effort. The Tela Authoring System can convert the netlists of a 360 cell library to deterministic gridded design geometries in two weeks with a 10%-15% reduction in chip area, according to Carney. Leakage and variability are also dramatically reduced for 45nm generation circuits.
Rather than restricting geometries, the Tela system is prescriptive: only certain things are allowed, but they are known to work. Thus the environment of every circuit element and cell is pre-defined by the “topology,” limiting context-dependent variation. The Tela process assigns one pitch and one orientation to all the lines forming the poly, metal1 and metal2 layers, avoiding “forbidden pitches” and other litho anomalies. Gaps in the lines define function. Since everything is placed on the grid, the vias are also on-grid, although not all grid sites are populated. Non-printing sub-resolution assist vias are placed at unused sites, facilitating the proper exposure of the desired contacts. Manufacturable implant geometries are also pre-defined.
 Figure 1. Conventional and 1D layouts as printed. (Source: Tela) |
Figure 1 compares a block laid out in a conventional way with one having the same function laid out in Tela’s grating-like system. The simpler linear shapes are printed with greater fidelity, according to simulations provided by Brion Technologies.
 Figure 2. Histograms of gate lengths shows reduced variation. (Source: Tela) |
Figure 2 illustrates the reduction in gate length variation due to the increased regularity of the 1D design. Since there are fewer short gates, leakage is reduced and circuit performance improved.
 Figure 3. Poly gate and implant levels of a typical block as laid out in 1D a), along with the full block with two levels of metal b). (Source: Tela) |
The circuit elements “snap” together (Fig. 3), making layout and timing generation more efficient. Carney claimed that complex logic elements could be created in less than an hour.
The linear topologies also lend themselves to separation into two masks, or sequential lithography and deposition processes, for the double patterning technology needed for the 32nm node. Co-authors from Tela and Applied Materials presented one paper on how gridded design rules could be implemented with a self-aligned spacer double patterning process that used Applied APF (advanced patterning film) to fabricate geometries suitable for 22nm node Flash, SRAM and logic cells.
Tela was founded in 2005 by Scott Becker (CEO), Dhrumil Gandhi (COO), and John Malecki (chief architect), all of whom have backgrounds that include work with IP pioneer Artisan Components (now part of ARM). Michael Smayling, former CTO at Applied Materials and Fellow at Texas Instruments, is Tela’s SVP of product technology.
The company just completed its second round of financing, following a first round in 2006 that enabled them to develop a proof of concept; total money raised is $5M so far, according to the company. Initial investors included Sand Hill Finance Company, Teton Capital, and Western Technology Investment. Later, Intel Capital and Asia Tech Investments added funds. Now it seeks to partner with library development teams and provide design services to the ASSP/ASIC industry. –M.D.L.
Brion powers up to meet DPT challenges at 32nm-22nm
At the opening of the SPIE Advanced Lithography Symposium, Brion Technologies unveiled a more powerful version of its Tachyon Computational Lithography platform and the release of Tachyon DPT, software that allows chipmakers to meet the low k1 requirements for memory and logic devices at 32nm and below.
Neal Callan, VP of product operations at Brion, described for SST the four key elements of the new Tachyon 2.5 hardware platform: 1) an upgraded CPU from dual-core to a quad-core; 2) faster aerial image computations; 3) moving more compute-intensive operations from the CPU onto the FPGA, which is also faster than in the previous generation; and 4) improved system-level communication and data-flow optimization.
Just upgrading to a quad-core CPU would typically achieve 1.7+?? improvement in speed. But with those four elements combined, Callan said the Tachyon 2.5 is able to get around 2.5?? speed-up per rack, with the same IT footprint as the 2.0 version. “Typically, if it took you 12hrs to run a cm2 OPC job (whether creation or verification) on a Tachyon 2.0, that number would drop down to ~4-5hrs on a Tachyon 2.5,” he said. The 2.5 is bit-by-bit compatible with the 2.0 version, so if an end user runs the same job on each platform, and the difference of the two jobs is evaluated, they will be identical, because the fixed-point calculations are thusly compatible, according to Callan.
The Tachyon DPT software supports both types of double-patterning being used: the litho etch/litho etch DPT, or the computationally simpler spacer DPT. Callan noted that there are two components needed to be able to do DPT: coloring algorithms and overlay-aware model-based stitching. “You need to do coloring–i.e., be able to differentiate which set of the mask goes on mask 1, and which set goes on mask 2,” explained Callan. “The coloring algorithm resolves coloring conflicts on a full-chip level.”
The software is also layer-aware–for example, a mask is not split over a gate, instead, the mask is split outside on a field where it’s less sensitive to overlay errors when the two masks are stitched back together. “When we stitch the two masks together, we have to make sure that they are less tolerant of the overlay shifts you get when you print one mask on top of another mask when there is an etch step in between,” said Callan.
“A user can input a nominal mismatch in the anticipated overlay between the two masks and the software will take that into account when it stitches them together.” The software also provides for density balancing between the two masks.
The company is not disclosing how many customers it has for the new software, but Callan acknowledged that the company is engaged with several customers on DPT at 32nm–in particular, with memory manufacturers. Hynix was quoted in the product announcement. “Hynix recognizes the industry-leading performance of Brion’s Tachyon DPT solution,” said Dong Gyu Yim, research fellow, Hynix R&D division. “Double-patterning will be part of our low k1 imaging techniques and will be instrumental in our plans to begin producing devices at 32nm and below.”
On the logic side, the primary applications for the new software are at 22nm. Callan said that Tachyon DPT combined with the company’s existing Source-Mask Optimizer (SMO) provides a comprehensive 22nm-enabling solution for both R&D and production.
Tachyon DPT is now available, and Tachyon 2.5 will be available in June. –D.V.
Gauda harnesses graphical processor units for OPC
Have you ever wished that computational lithography could be more like a video game? Gauda, a Sunnyvale, CA, startup that decloaked at the SPIE Advanced Lithography Symposium, is offering to make it so, at least for optical proximity correction and verification (OPC and OPV).
 OPC/RET work is increasing faster than CPU capabilities. |
The idea, explained founder, president and CEO Ahmet Karakas in an interview with SST, is to use the graphical processor units (GPUs) in commodity desktop PCs to do the heavy lifting for litho simulation, just as they do for videogame graphics. While some tasks (i.e., full-chip OPV) will run fast enough with Gauda software on one PC, a simple Ethernet connection enables operation of a cluster. Ten Ethernet connected commodity PCs with GPUs can do OPC decoration as fast as the industry-leading system with its FPGA-based hardware acceleration, he said. When there is no computational engineering to do, the cluster can revert to its usual role, running business software and videogames.
Gauda CTO Ilhami Torunoglu reported that the company’s software has run model-based OPC faster and as accurately as systems based on server farms or specialized hardware. Input and output for post-processing tasks can be in the form of GDSII or OASIS files. Unlike systems that require flat input files, Gauda software can process hierarchical data. Beyond OPC, he claimed that the Gauda software also enables etch process verification (EPV) and printability checking. The core innovation was the use of parallel computing algorithms to enable efficient operation of one or many GPU equipped PCs. “When the Gauda application is running, the GPUs do most of the work, leaving most CPUs available for word processing and other tasks,” reported Torunoglu.
Because commodity PCs are so inexpensive and useful for other applications, Karakas believes that Gauda’s computational lithography system will be adopted for RET tasks in design shops as well as in manufacturing environments. The first beta sites, however, are at IDMs, he reported. While the OPC for a 45nm chip layout will run overnight on a 20 PC system (costing perhaps $300,000), adding PCs adds speed linearly at low cost, enabling even more advanced future designs. –M.D.L.
Molecular Imprints announces 4WPH step and flash imprint tool
Claiming the ability to print 32nm, 28nm, and 22nm features at 4WPH with 35nm overlay, Molecular Imprints, Inc. (MII) says its latest imprint lithography tool for semiconductor applications, the Imprio 300, introduced at the SPIE Advanced Lithography Symposium, is the “only game in town” for semiconductor prototyping and process development in the <30nm realm.
“Our unique technology imprints into liquid at room temperature, facilitating overlay,” according to CEO Mark Melliar-Smith, who discussed the technology in an interview with SST. The step-and-flash tools are drop-in replacements for optical exposure tools, completely compatible wit current processes.” He provided slides showing that working FinFET transistors have already been patterned at 20 and 30nm and resist CD uniformity demonstrated at 0.8nm with LER <2nm.
Molecular Imprint’s stepping tools dispense the resist as droplets with density scaled to the local duty factor inside each imprint field. That results in a highly uniform residual resist layer after imprint, which, they claim, can be removed using standard descum processes.
The Imprio 300 is targeted for memory applications where circuit density is paramount. For NAND flash architectures, density and cost-of-ownership trump overlay, perhaps opening a niche for imprint lithography, according to Melliar-Smith. Over small fields, however, the Imprio 300 claims an overlay precision (mean +3σ) below 10nm. He estimated that the throughput of the Imprio 300 would make its CoO compatible with that of 193nm immersion and less than EUVL prototypes. Experience with previous-generation tools also led Molecular Imprints to improve the graphical user interface and operator features of the Imprio 300. First shipment of the new system is scheduled for mid-2008.
Melliar-Smith also discussed Molecular Imprints’ roadmap to make the company the world leader in sub-30nm lithography for flash memory. A high-volume manufacturing tool with 15nm overlay and 20 WPH throughput is on track for introduction in 2010. At the 22nm flash node, that tool would be less expensive to operate than EUVL or spacer-type double patterning, in part because of its use of replicated templates. He also predicted that the disc drive industry will be ramping up patterned media production in 2010. In that technology, one disc will hold 1013 30nm posts (on each side), each post corresponding to a bit of data. Molecular Imprints is developing high-throughput tools based on their Imprio 1100 technology for that full-field application.
Melliar-Smith counted 12 papers at the symposium as evidence of the increasing acceptance of SFIL. –M.D.L.