Imprint litho forms arrays for new fault-tolerant nanoscale circuits
04/01/2008
EXECUTIVE OVERVIEW
Extending Moore’s Law to 22nm and beyond for logic circuits calls for new concepts in manufacturing processes and device architectures. Fault-tolerance is critical to manufacturing on molecular scales. Nano-imprint lithography (NIL) technology has been shown to produce regular arrays of lines down to 17nm half-pitch. NIL defined arrays can be used to form cross-bar circuits that provide redundant connections for both interconnect and logic functions. Semiconductor nanowire interconnects (SNIC) based on the cross-bar architecture may be integrated with traditional CMOS circuits to create a hybrid field-programmable gate array (FPGA).
We can never plan for the unexpected, and so it is difficult to predict the results of pure research into the frontiers of scientific knowledge. The development of solid-state electronic devices based on semiconducting crystals such as silicon has been extended to nearly unimaginable scale by the integration of circuit elements by photo masks into the same chip. By 1965, Gordon Moore had first told the world about his observation of the number of circuit elements per chip doubling regularly. Moore himself acknowledges that “so called Moore’s Law” (as he always refers to it) was originally just a marketing tool used to convince people that cost-per-function would decrease regularly for ICs, so that new high-volume applications could be developed.
In his landmark interview in Solid State Technology (“Moore’s Law extended: The return of cleverness,” July 1997), Moore discussed the cost and functionality factors which have driven ICs into new markets. “What`s driven the industry is lower cost. The cost of electronics has gone down over a million-fold in this time period, probably ten million-fold, actually,” said Moore. “While these other things are important, to me the cost is what has made the technology pervasive. I’ll hate to get to the point where we don’t get the speed improvements also, but that may happen for such things as power limitations going forward.”
In December 2007 at IEDM, an evening panel discussion on the future of commercial ICs explored possible new materials and device structures to replace the CMOS FET. Possible new materials could be compound semiconductors and carbon nanotubes (CNT) and graphene, while new devices which are known possibilities include silicon nanowires (SNW) and quantum dots. The consensus of the world’s leading researchers seemed to be that none of these technologies will be able to provide greater functionality and reduced costs in the near term. There was, however, one new direction which seems very promising and has been demonstrated in a lab: the Hewlett-Packard cross-bar architecture formed by NIL.
Manufacturing fundamentals beyond CMOS
One of the paradigms of complementary metal-oxide semiconductor (CMOS) IC fabrication is that the circuits need to be nearly perfect. Except for the redundancy of doubled metal vias between different levels of on-chip interconnects, traditional circuit functionality cannot tolerate shorts or opens in lines. As the size of conventional IC structures shrink to molecular scales, the “process window” has correspondingly shrunk such that the cost of ensuring near zero defects in manufacturing has risen exponentially.
In 1994, HP Labs showed the Teramac computer built with known defective FPGA chips, and using a reconfigurable, redundant data routing network to permanently route around defects. Teramac handled a 3% defect rate, since ~220,000 of the 7 million resources were bad. This proved that re-routing and FPGA architectures have the potential for defect tolerance. HP has also shown that up to 50% of circuit elements can be defective without killing complete functionality, though so far only with a severe speed penalty.
Prof. K. K. Likharev (Stony Brook University) first conceived of cross-bars directly on CMOS circuits. This shrinks the memory by 9 times, increasing the density (and thus speed) of the circuit. However, HP researchers felt that Likharev’s concept was not manufacturable, because protruding pins would be difficult to contact, and overlay would be an inherent manufacturing issue.
Compared to the Likharev circuit architecture, HP chose to sacrifice some density to allow for larger connect pads between layers and easier overall integration. Using CMOS as the underlying logic layer, HP then creates a cross-bar array formed with a bi-stable switching layer sandwiched between perpendicular top and bottom nanowires patterned by NIL. This semiconductor nanowire interconnect (SNIC) architecture has high defect tolerance and can be integrated with CMOS to form a new type of circuit that performs like an extremely high-density field programmable gate array (FPGA).
The SNIC has several advantages, however, over conventional ICs and FPGAs. Because the memory cells are in a cross-bar array, defects can be routed around and the circuit is highly defect-tolerant. The memory layer is placed directly above the CMOS circuit, thus leading to better access and higher speed.
Most importantly, because the architecture is inherently defect tolerant, NIL can be used to fabricate the memory layer. Tight pitch structures may be fabricated by NIL, yet defects and overlay issues remain in trying to integrate NIL with traditional process flows. By designing fault-tolerant circuits, NIL can be used at a lower cost than alternate next-generation lithography (NGL) solutions such as EUV.
Nano-imprint lithography
NIL is a classic disruptive technology according to William Tong of HP’s Technology Development Operations (TDO), in that it starts out as a relatively lower technology approach to patterning but can be cleverly extended to provide capabilities rivaling the most expensive extensions of the established technology. For example, HP has successfully developed several different NIL integration flows, working with Molecular Imprints. While there are many commercially available NIL technologies, HP continues to invest in the field by doing both in-house development and working with commercial vendors.
Wei Wu leads the HP Labs research on new NIL technology, and he emphasizes that NIL is intended to be a relatively low-cost patterning approach. Consequently, while overlay accuracy is a known issue with any NIL technology–since overlay accuracy is currently far worse than basic resolution–any overlay accuracy issues must be resolved without high cost. It is very difficult for mechanical components to move over microns of scale while maintaining nanometers of accuracy, and so Wu’s team developed a clever two-part alignment process using low-cost tooling.
 Figure 1. Wafer bending nano-imprint approach. |
Figure 1 shows the step and imprint technology developed internally by HP Labs. The mold is fabricated with metal “stands” at the periphery, allowing for rapid coarse alignment and coupling to the wafer. These metal spacers are fabricated using standard semiconductor processes, and leave ~1??m z-spacing between the resist and the mold. Then the fine alignment is done. Backside air pressure to the wafer and/or to the mold bends the surfaces together to do the imprint step. Step and repeat works well with the spacers touching down only in the streets between chips.
The advantage is that there are no moving parts to lose alignment after the wafer has been brought into contact with the mold. Only the wafer or mold bends, and those mechanical forces, are known and controllable. Can the wafer bend sufficiently to allow for such processing? If the imprint field is 1 in. ?? 1 in. and the nearest spacer is ~0.5 in. away from the center, then this represents ~4 orders of magnitude greater distance in x-y than the ~1??m travel needed in the z-direction, which is more than sufficient to allow for patterning. The lateral shift with this technique is reportedly <2.4nm with the current setup; if this shift becomes an issue, then the spacer height or imprint field geometries can be adjusted accordingly.
With minimal mechanical challenges, and with the center of the field in contact first after the two-part alignment, the NIL tool can be small and compact and perform both the alignment and the NIL step itself. HP designed this NIL hardware specifically to work as a modification to a SUSS contact alignment tool. Their lab prototype shows better than 0.5??m alignment accuracy for two successive NIL layers, though this was limited by the optical alignment of one particular SUSS tool. This technology has been licensed to NanolithSolution in a nonexclusive global license. The company now sells NIL tools that are compatible with mask aligners from several manufacturers.
 Figure 2. Nanocrossbar circuits at 30nm half-pitch by nano-imprint at HP (AFM image). |
Figure 2 shows an atomic-force microscope (AFM) image of 30nm half-pitch orthogonal NIL layers used in a laboratory prototype memory circuit. To improve alignment, HP developed a nanodisplacement sensing and estimation (NDSE) technique using technology originally developed for paper positioning in a large-format printer. They can achieve 1/50 pixel size resolution for displacement sensing using an inexpensive digital camera to image the area of interest.
NIL of interconnect arrays
The cross-bar architecture provides a new way forward for IC structures. The original concept was explored with complex organic molecules as the switching elements between cross-bars, but currently available molecules lacked parameters for manufacturing so inorganic switching materials have been explored. The electrical properties of the desired switch material typically determines the possible metals that could be used for the upper and lower contacts.
 Figure 3. Nanocrossbar circuits at 17mn half-pitch by nano- imprint at HP (SEM image). |
Initial published work on metal oxide as the switch material has shown that it exhibits hysteresis and the ability to be reversibly programmed. The exact mechanism by which reversible behavior occurs has not yet been conclusively proven, but empirical data show that the noble metal contacts work best. For those switches, platinum (Pt) has been used as the metal for both the upper and lower nanowires. Figure 3 shows that HP has already formed 17nm half-pitch cross-bar arrays, and smaller geometries have been conceived.
Clearly, there is strong motivation to integrate cross-bar switch arrays with CMOS circuitry into hybrid circuits which could be readily fabricated with presently established high-volume semiconductor manufacturing technologies. For integration with aluminum (Al) and tungsten (W) metals used in standard CMOS interconnects, Al cross-bars would be ideal, but Al does not work with certain switching elements. Consequently, bi-stable alumina (Al2O3) has been developed as a switching material at HP’s TDO, though with the limitation that it is irreversible. Still, one-time programming allows for field-programmable gate array (FPGA) functionality, and the density of the NIL defined cross-bars still represent a leap forward compared to conventional FPGA architectures.
 Figure 4. A new type of circuit that performs like an extremely high density field programmable gate array (FPGA). (Courtesy: Greg Snider, HP Labs) |
A custom CMOS circuit, designed and fabricated at HP Corvallis, is capable of providing a voltage of 0.5 to 7.0V to provide maximum flexibility in accommodating different possible switching materials. The same group develops the overall process flows needed for integration (Fig. 4). Prior to being patterned, the lower Al film was blanket deposited onto the wafer without further treatment of the tungsten (W) vias connecting to the underlying CMOS circuitry. The Al was patterned with 200nm half-pitch nanowires by a Molecular Imprint Imprio 100 nano-imprint tool using the S-FIL/R process. A 248nm DUV resist layer is used as the transfer layer to achieve higher etch selectivity.
SNIC based on Al cross-bars seems to be preferable over the Pt in terms of conductivity, which is a bottleneck as chips scale to ever smaller dimensions. Since the resistivity of Al is ~4?? lower than that of Pt, the former metal is more desirable for nanoscale wires.
 Figure 5. Al nanowires in contact with the W contact (round). (Courtesy: Laura King, Mike Cumbie, Jim Ellenson, HP Corvallis) |
The hybrid interface between the photo-defined W vias and the nano-imprinted Al wires has been studied (Fig. 5). Two types of electrical testing were carried out successfully to demonstrate integration. HP measured the average contact resistance between an Al nanowire and a W contact plug to be 0.81Ω (4-point), which is very low compared to the resistance of the Al nanowire itself. HP also demonstrated serial continuity by using a focused ion beam to make selective cuts in the cross-bars so as to route the current through 6 vias in series; the resistivity was found to be ~180Ω, which is within the 95???185Ω expected range.
Conclusions
Cross-bar architectures have been developed to provide both reversible and one-time programming, for integration with CMOS into hybrid FPGA-like circuits. Conceptually, this may be considered as a low-cost FPGA that allows for leaps ahead in circuit density.
Fault-tolerance has been shown, which allows for the use of relatively low-cost NIL for patterning. The architecture does not require excellent overlay nor low defect levels to work, so it gets around the traditional semiconductor manufacturing paradigm that devices have to be perfect.
In addition to their functionality as interconnects, cross-bar arrays may be used as the building blocks of new logic circuits. The NIL templating capability has also been shown in the creation of negative-index-of refraction meta-materials. As Richard Feynman observed, “There’s still plenty of room at the bottom.”
Acknowledgments
Many thanks to Wei Wu and Stan Williams of HP Labs, Quantum Information and Systems Lab, for leading the NIL technology development and for discussion with the author, and William Tong of HP for leading the SNIC integration team in Corvallis, Oregon. DARPA funded some of the R&D. Step and Flash and S-FIL are registered trademarks, and SFIL/R is a trademark of Molecular Imprints.
Ed Korczynski, senior technical editor, received his degree in materials science and engineering from MIT in 1984, and worked in process development and integration in fabs. He has held process applications, marketing, and business development roles at equipment providers, and won editorial awards for SST interviews with Gordon Moore and Jim Morgan. He writes the weekly e-column Ed’s Threads at www.pennwellblogs.com/sst/eds_threads/. He can be reached at [email protected].