Technology news
03/01/2008
Shedding light on alternative to LCD manufacturing
Replacing traditional TFT-LCD manufacturing with a lower-cost alternative that is also a more efficient technology is (forgive the pun) a bright idea that should be attractive to manufacturers. Uni-Pixel is aiming to fulfill this wish with its time-multiplexed optical shutter (TMOS), a thin-film membrane (Fig. 1) that oscillates in and out when in contact with a lightguide. Leveraging support from Philips’ open innovation center in The Netherlands, Uni-Pixel recently announced the successful assembly of six display prototype devices.
 Fig. 1. Micrograph of TFT backplane with Opcuity film bonded on top. (Source: Uni-Pixel) |
Unlike TFT-LCD technology in which the panel is back-lit, TMOS panels are edge-lit (so the light source is on the edge), company CFO Jim Tassone told SST. In a TMOS system, light is injected into the lightguide (or a sheet of TFT mother glass) and maintained in the lightguide by way of total internal reflection (TIR) (Fig. 2). “By injecting light into the lightguide, our objective is to create a uniform dispersion within it, and we ensure that the coupling at any given pixel is detuned so that individual pixels do not extract too much light too early,” he said. “Each individual pixel’s coupling efficiency is tuned down to a level where it allows light to travel throughout the lightguide without being lost too early, or too much, at any given point.”
 Fig. 2.Conceptual cross-section of a single pixel actuated during a red sub-frame. Source: Uni-Pixel. |
Control over the maintenance of the TIR angles over time is achieved by precision injection in the z-dimension (the lightguide/glass plane forms the x/y dimensions), Tassone explained. Some light is lost due to scattering, but at insertion the light is controlled at specific angles and maintains them as it travels through, until it finds an open pixel, couples out, and is extracted to the viewer.
While there is some degradation (loss of light over time and distance traveled within the system), the individual light bursts are in such a short amount of time and are exhausted very quickly, that the amount of degradation is not significant enough to affect the overall performance of the system.
According to Tassone, a TMOS system is ~61% efficient, meaning that ~61% of the light that is injected into the system is ejected. “Because of the detuning of the individual pixels, any given light photon ensemble will only lose a portion of its energy in the first bounce,” he explained. “That ensemble, or portion of that ensemble, is available to pixels downstream, so it’s a multi-pass system where light is recycled until it is used or exhausted.” In contrast, today’s LCDs are about 5%-8% efficient, meaning that ~5%-8% of the backlight makes its way through the system to the viewer in a single pass, he noted. The company’s models show that a TMOS system can be tuned to get an efficiency >61%, but uniformity is adversely affected as a result, Tassone noted.
A major advantage of a TMOS-based panel is that polarizers, color filters, and liquid crystals, which make up a significant portion of the bill-of-material (BOM) costs, are not needed. Tassone said the company’s model shows that, depending on formfactor, its technology can achieve 40%-60% lower BOM costs than an LCD panel.
Manufacturing TMOS
The thin film itself is made up of a carrier substrate, similar to a mylar PET film, although the company is also examining other materials. Micro-optic structures are added to the thin film followed by a conductor layer. “Each individual pixel is a “drumhead,” and mating the thin film to the TFT glass creates the “drum”-so the MEMS structure is the drum created by adding the thin film to the mother glass, explained Tassone. “That thin film is now complete in the sense of what a manufacturer needs to integrate it into a panel,” he said.
Because the TMOS-based panel uses a limited number of LEDs for light insertion at the edges, the panel is power efficient-models show on average, ~90% less power consumption than in an LCD system, said Tassone. “So you have a much higher light efficiency in transmission at a much lower power.” An example of how this combination would be useful is in a handheld device, where a daylight-readable cell phone could still consume very little power, thereby extending battery life.
Two key challenges were over‑ come in the TMOS prototypes and will be further optimized as the company develops a volume manufacturing process: ensuring a sufficiently low pixel-drive voltage, and stiction mitigation. The capacitor structure (the conductor on the thin film and the conductor on the TFT glass) is driven by the voltage differential, which creates the Coulomb attrac‑ tion that actuates the pulling action on the thin film. “At the individual pixel level within this capacitor structure, the distance between the conductive plates is directly tied to the voltage required to drive the pixel,” noted Tassone. “The challenge is making sure these two conductors are close enough so that the voltage is low enough to be compatible with current TFT manufacturing.” The company says it has created a system in which the two conductors are close enough so that the voltage required to actuate is <20V. “If you look at LCD manufacturing, there are falloffs in yield if there is an actuation >20V,” noted Tassone.
With respect to overcoming stiction, Tassone told SST that a “little bit of stiction is good” as it provides for good light coupling (when the thin film is in contact with the lightguide). However, stiction has to be overcome when the membrane needs to be released so the device can go into the off-state. He said the company’s prototypes show that its methods overcome stiction, and the challenge now is to migrate them into high-volume manufacturing, “and we believe we have a path to do that.”
The business model
Uni-Pixel plans to license the overall architecture and various aspects of the subsystems, and will also supply the single thin film. The films are delivered to the company’s licensees in either sheets or rolls; alternatively, fabs/panel manufacturers can license the recipe. TMOS-based panels can be built in existing LCD fabs using existing TFT-LCD equipment.
The company is currently negotiating with licensees and also considering JDPs with various LCD manufacturers. “These agreements will allow us to place projects into R&D development fabs that will allow us to transition to production fabs,” said Tassone. “The timeline for roll-out will be tied to these agreements.” The company is targeting having systems enter the market in late 2009, and “we see no significant hurdles toward compatibility with production,” Tassone said. -D.V.
Japan’s PV suppliers tout improved efficiencies
Revealing the first details on its CIGS technology, Honda Soltec Co. Ltd. says it’s averaging 11.1% efficiency from its new solar module line. Other leading Japanese photovoltaic suppliers also described technologies for improved efficiencies now starting to move into production, reports SST partner Nikkei Microdevices, from the recent 17th International Photovoltaic Science and Engineering Conference in Fukuoka, Japan.
 Honda’s CIGS process relies on high temperature selenization, a sodium spray coat, and a buffer of InS. (Source: Honda Soltec, Nikkei Microdevices) |
Honda’s solar subsidiary said the key to its relatively high-efficiency volume CIGS thin-film production (see figure) is increasing the selenization temperature to more than 500°C for better crystal quality. This requires low-alkali, high-temperature glass, though it lacks the sodium that typically aids in crystallization. But, it turns out that the auto paint guns in Honda’s new plant are being used to spray a sodium solution on the glass, to add back the Na to enhance the crystallization process. Honda also bypasses Cd issues by replacing the usual CdS buffer layer with InS. The company notes best results from its pilot line are 12.2% efficiency.
The company developed its own PV technology in-house, initially aiming primarily to be able to efficiently generate the energy for making hydrogen to power its fuel cell vehicles and power its own factories. In fact, the solar cells have been installed at Honda’s demonstration hydrogen refueling station Los Angeles, and at some of its factories. Residential solar modules also are being marketed in Japan from its new plant in Kumamoto, slated to ramp production to 27.5MW by this spring.
Mitsubishi Electric Corp. reported increasing its polycrystalline silicon cell efficiency to 18% with a cluster of innovations moving into production. It roughs up the surface to cut reflectivity and increase absorption of light by reactive ion etching through a quick and cheap mask layer of a coating of 3µm silica particles in solution that self-assemble into the texture pattern. The company also terminates the dangling silicon bonds with hydrogen, and uses an undisclosed new circuit material and modified screens to reduce the size of the circuit lines on the cell surface, reportedly cutting metallization time about in half and reducing shading loss by 40%.
Sanyo Electric Co. Ltd., meanwhile,. reported its cells made with its heterojunction with intrinsic thin layer technology (HIT) are now up to 19.7% efficiency in production, and 22.3% in the lab, and said it has developed a 20%-efficient version using 70µm thin wafers. These cells, made with a low-temperature 200°C process, coat a crystalline silicon wafer with thin amorphous silicon layers on both sides, which reportedly improves boundary characteristics and reduces power losses by forming impurity-free i-type silicon layers between the crystalline base and the n- and p-type amorphous silicon layers, while allowing use of thinner wafers. Sanyo said it plans to increase its production from the current 260MW to 650MW by 2010.
The company also noted progress on its thin-film deposition technology, claiming its localized plasma confinement CVD method was now depositing multicrystalline silicon film on 550mm × 650mm substrates at 2nm/sec, with ±3.3% uniformity. A key step was miniaturizing the pyramidal nozzles to create a uniform plasma. Though the company did not disclose efficiencies on the larger substrates, it has previously reported efficiencies of 7.6% in polysilicon films made by the process on smaller substrates.
Sharp Corp. showed off a 1cm2 organic cell rated at 3.8% efficiency by Japan’s National Institute of Advanced Industrial Science and Technology (AIST). Some other organic photovoltaics have reached 5% or so, but only over areas of ≤0.2cm2. The researchers used P3HT [poly (3-hexylthiophone)] for the p-type semiconductor, PCBH ( [6,6]-phenyl C61 butyric acid methyl ester) for the n-type. Key to the improved performance, they said, was improving the alignment of the P3HT polymer chains.
Sanyo also released the first details of its work on organic solar cells, where it is getting 3.6% efficiencies using small molecules and fullerenes, albeit on tiny 0.033cm2 samples. Though much work on organic photovoltaics has focused on polymers that presumably could be very cheaply applied by wet coating, the Sanyo researchers argued that work in OLED displays had convinced them that small molecules will be the more effective material. It’s using its OLED material DBP (tetra- phenyldibenzoperiflanthene) for the p-type semiconductor and C60 for the n-type.
Sharp also claimed a major improvement in a concentrating solar cell system, with 40% efficiency in a 1000× concentration system, using a 4.5mm2 InGaPAS heterojunction cell. It said 40% efficiency has previously been reported only up to 200× concentration. -Paula Doe, Contributing Editor
TEL ready for solar debut
Separately, Tokyo Electron chairman Tetsuro Higashi told Nikkei Microdevices that his company plans to enter the solar equipment business with a thin-film deposition system, rather than the turnkey lines currently supplied by most equipment makers. “The technology is changing so fast now that one really needs to work with the users to understand the product to improve the process,” he said. “We’ll work closely with users to move gradually into the market.” Higashi said the company “decided to focus first on strengthening our core business before investing in solar,“ seeing an opportunity to grow the semiconductor business to catch up with AMAT. -P.D.
SMC highlights PV, LED, and packaging materials
This year’s Strategic Materials Conference in late January showed truly amazing perspective on new electronic materials markets of gigantic scales like photovoltaics, high-efficiency lighting, and advanced 3D and WLP packages.
Solar is hotter than the sun these days, and Craig Hunter of Applied Materials provided a great overview of the whole market. The global market in 2007 for PV panels was reportedly 4.8GW, up ~50% from 2006. The current approximate cost to install a rooftop solar PV system is US$0.25-0.30/kWhr (absent incentives). However, nearly all PV manufacturers show near-term roadmaps to cut PV fab costs in half, and there are additional innovations possible in installation of modules, so it seems likely that price could drop to US$0.10-$0.12/kWhr for large scale installations without any incentives. With demand forecasted to be extremely elastic to price, and with total global energy use growing at 2%/year on the scale of terawatts, PV growth will likely remain <1%.
 Applied Materials’ SunFab PECVD 5.7 multi-chamber deposition system for PV on huge glass panels. |
The future of mega-fabs for PV panels includes integrated supply-chain campuses like the classic old Ford Rouge Plant in the 1920s. The thin-film PV fab of the future will be more efficient when it has a dedicated float glass plant for the substrate, a line for the thin-film encapsulant formation, and even packaging of the junction-boxes for the final modules. Each of these may be owned by a different company, but for economies of scale and manufacturing efficiency they’ll be adjacent to each other. Process gases such as hydrogen, silane, etc. account for ~17% of final panel costs, so long-considered innovations such as silane reclamation may be used in manufacturing. In general, it seems that the main scientific breakthroughs in PV have been made, and now the best engineers will win the race to fab profits.
George Craford, CTO of Philips Lumileds Lighting Company, discussed the imminent “Revolution in lighting, high power LED technology.” As a demonstration, Buckingham Palace has been externally lit by LEDs at a cost of US$0.45/hr. The theoretical light output limit for an LED is 300 lumens/W, but the best in production is ~100 lumens/W, with 150 lumens/W on a roadmap. The plan is for high-power LEDs to be 1-3 per replacement bulb.
From the 1960s through the 1990s the LED brightness evolved at a fairly constant rate, though this was based on driving the same size chips with the same power. Starting ~10 years ago, the industry began to work with new packages to allow driving higher current-densities and resulting higher outputs for applications include automotive, flashlights, and projectors.
The potential energy savings with LEDs is truly impressive. Incandescent bulbs require 60W of input power to get 1000 lumens output, with roughly $48/year in energy costs, extended to a five-year CoO of $240. The cost profile gets progressively better for fluorescent tubes (20W input power, $18/yr, $90/5yr) and compact fluorescent (14W, $13, $85). LEDs, meanwhile, require one-tenth the input power (6W) and reduce energy costs by 90% vs. incandescent bulbs ($5/yr, $26/5yr).
So why aren’t white LEDs everywhere? Quite simply, the cost has been too high. For the same 1000 lumens output (60-100W incandescent bulb equivalent) the incandescent bulb costs $0.40, fluorescent tube $0.60, compact fluorescent $2, and white LED $10. Lumileds researchers seem confident that they can improve the basic internal quantum efficiency from ~45% today to ~90% tomorrow, and with higher drive current (700mA to 2A) and lower chip and packaging costs, the cost could be ~$1.
Control of manufacturing is a concern since the variation in blue wavelength crossed with the yellow phosphor materials distribution creates variation in the color of white. The human eye is sensitive to subtle color variations and tight matching is needed for LEDs in the same room. Off-grid applications can be valuable using a single LED with a solar array or a bicycle generator. For example, the Light Up The World foundation has been installing LEDs around the world to allow children to be able to study schoolwork at night. China estimates that by changing to LED lighting it will save them as much electricity as the maximum planned output of the Three Gorges Dam. “They are going to dominate conventional illumination. It’s only a matter of time,” said Craford.
Packaging technology for ICs continues a steady evolution, with few examples more telling than the wire bonder. Wire bonders have periodically been considered as limited, but they evolve and now can go to five or even eight levels of silicon using new materials for dielectrics and interposers. Flip-chip, which has been used almost exclusively for MCUs, is finally moving into the mainstream in combination with wire bonding and leadframes to allow for many efficient high-volume packages-but SiP and SoC will continue to coexist in many possible variations using flip-chip and wire bonding. Package-on-package approaches also remain competitive, with variations using thinned silicon, recessed-cavities, and fan-in routing. -E.K.
Ponte Solutions sees advantage in taking DFM to the IP level
Several announcements involving Ponte Solutions during the final months of 2007 illustrated a strategy of targeting DFM at the IP level by placing tools in the hands of designers where they are most comfortable: in the “cockpits” of their favorite EDA tools (e.g., Cadence’s Virtuoso platform, Pyxis’ Nexusroute yield-driven IC router, and Silicon Canvas’s Laker layout software). The company’s strategy is also grounded in the fabless/ foundry business model. For example, a typical foundry would have to win as many as 1000 designs to get a return-on-investment, Michael Buehler-Garcia, Ponte’s VP of marketing and business development, explained in an interview with SST. “That’s about 4× more than an IDM needs for the same size fab, but chasing so many designs means engagement with hundreds of companies,” he said.
With so many different designs and companies in the mix, though, the generic foundry design rules and DFM recommendations have to be very conservative. So Buehler-Garcia’s advice to the fabless companies is to own the DFM challenge. One way to enable DFM ownership is to provide designers of IP (e.g., standard cells, custom IP blocks, memories, etc.) with actionable critical-area analysis (CAA) information so that they can minimize the impact of the most critical CAA effects, as predicted by foundries’ certified defect kits. Interfacing Ponte’s YA System with Cadence’s Virtuoso platform and the pairing with Silicon Canvas’ Laker Layout software were two implementations of this strategy.
Sedrak Sargisian, VP of engineering at Ponte Solutions, explained to SST that if an IP offering is “DFM-robust,” it can have an impact across multiple designs. “Whereas DFM corrections at the metal layers are generally applicable only for a specific design,” he said, “DFM analysis needs to be done as part of the overall design process, not only as a post place-and-route check.”
Also on Ponte’s plate has been participating in the Silicon Integration Initiative (Si2). The company has been working with Blaze DFM (whose acquisition of Aprio’s technology was particularly significant) to deliver yield and lithography modeling elements to the Si2 specification. The company also is contributing to Si2’s CMP specification with other Si2 members Praesagus and Cadence to synchronize their efforts.
Next on Ponte’s agenda is completing a physics-based etch modeling for vias/contacts and poly/metal. “The current rule-based etch bias can no longer ensure delivery of designs capable of being consistently manufactured in a nanometer fab,” said Ponte CTO Ara Markosian. “The impact of pattern density variability on etch-induced pattern transfer must be considered, accurately modeled, and corrected at 45nm and beyond.” Indeed, etch was listed as a critical concern moving into and beyond 45nm by all companies attending a recent DFM session held between the DFM Coalition of Si2 and various customers of STARC and the Common Platform, according to Jake Buurma, VP of operations at Si2.
The company’s etch solution was in beta evaluation with a major Japanese IDM during 4Q07, with additional evaluations to occur in 1Q08 when the product is released to the general market, according to Buehler-Garcia. -D.V.