Intel pushes lithography limits, co-optimizes design/layout/process at 45nm
03/01/2008
EXECUTIVE OVERVIEW
This month, SST presents a preview of the March edition of Chip Forensics, an SST online column by Dick James, senior technology adviser at Chipworks, a specialty reverse engineering company that takes apart ICs and electronics systems in order to provide engineering information for its customers. In this column, James details some of the groundbreaking techniques used by Intel in the manufacture of its Penryn chips.
In one of the most hyped chip launches in recent times, Intel launched its 45nm, high-k, metal-gate (HKMG) Penryn series of chips last November. Some details have been published recently on the HKMG process [1, 2], so I thought that I would discuss some of the other ground-breaking techniques used by Intel in the manufacture of the chips.
At the International Electron Devices meeting (IEDM) last year, there was a one-day short course called “Performance Boosters for Advanced CMOS Devices,” and the last session of the day, on Device and Circuit Interactions, was given by Paul Packan of Intel. Within this, there was a discussion of design for manufacturability (DFM-one of this decade’s main foci for the industry). In addition to the usual details on lithographic and design rule enhancements, there were a couple of slides showing how inserting dummy devices to give a regular layout and optimize pattern density can reduce variability, and improve manufacturing parameters such as the temperature distribution across a wafer during thermal processing.
A couple of days later, Kelin Kuhn gave her paper, “Reducing Variation in Advanced Logic Technologies” [3], which went into more detail about some of the layout and process changes used to limit, and even improve variation in 45nm parts compared with their 65nm predecessors.
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I mention these presentations because after seeing them, it clarified the reasons for the extraordinary layout that we found when we analyzed Intel’s 45nm Xeon processor last fall. However, let’s look first at the improvements in lithography seen in the 45nm process, since Intel has stayed with dry exposure when others are moving to wet lithography tools. The table lists the pitches of the different levels that we found in our analyses.
 Figure 1. Plan-view SEM images of M3 level in Intel Xeon and Yonah. |
Figures 1-4 show images of the SRAM array from the Xeon (left), and the 65nm Yonah chips, going down from the metal 3 (M3) level to the gate level. At all the metal levels we can see that, contrary to intuition, the edges are much crisper and line edge roughness is reduced. (In the Xeon-M2 sample, there has been some movement of the lines due to our sample prep.)
 Figure 2. M2 level in Intel Xeon and Yonah. |
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 Figure 3. M1 level in Intel Xeon and Yonah. |
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 Figure 4. Polysilicon level in Intel Xeon and Yonah. |
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 Figure 5. Intel images of SRAM poly. |
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In the gate images, the edges are not as well defined, but the sidewall spacers are also present-we cannot see the actual gate edges. The tungsten M0 level is also present in the Xeon sample to add to the confusion. The Intel images (Fig. 5) of polysilicon from the IEDM paper are a bit clearer, and show similar impressive changes.
Intel has clearly put a lot of work into improving their lithography processes, especially as they continue to use dry exposure. Here I use “lithography” in its classical sense, to include the etch and CMP processes-after all, if you buy a lithograph print, you buy the finished print, not the intermediate masking stage before the ink goes on the paper; and it is the final, defined features that form an IC.
Intel has stated that it uses double patterning at the gate level, and dual APSM (alternating phase-shift masking) in their 45nm processing. Design rule changes have been made at the lowest levels to minimize any orthogonal patterning; in the SRAM, the only right-angle features are in the M0 local interconnect. The 45nm test chip announced in January 2006 was used to confirm the results of the computational lithography and DFM simulations employed to co-optimize the products and process.
The squaring of the gate electrodes is presumably produced as the result of the optimized APSM and the double patterning; we have also seen this in the latest Flash memory parts, so it is becoming an established technique. Double patterning effectively doubles the k1 factor (critical dimension = k1 × λ/NA), taking the pressure of the resolution limits. Even so, the reduced pattern variation given by the increased spacing of the electrodes at each patterning step has to be an overall benefit when compared with the increased cost of the process, and extra challenges such as controlling the overlay between the steps. The actual benefit is to reduce the variations caused by “dog-bone” and “icicle” endcaps, and this should contribute to an improvement in the cell mismatch [3].
 Figure 6. Plan-view TEM image of gates in SRAM array. |
Of course, we were curious to see how well the actual product compared with the sacrificial polysilicon pattern shown in Fig. 5. The SEM images cannot give us enough detail because, as a surface imaging technique, it cannot distinguish the spacers from the metal in the gates. Figure 6 is a plan-view TEM image of a pair of combined pMOS/nMOS gates from the SRAM, and they have kept the square profile fairly well through the polysilicon etch, metal deposition, and CMP steps required to make the metal gate structure. The pMOS transistors are distinguished by the mottled texture of the titanium nitride used in the pMOS gates, as opposed to the aluminium fill used in the nMOS. The sidewall spacers can be seen as a faint ghosting around the gate electrodes.
 Figure 7. TEM Images of metal gates. |
However, if we look outside the SRAM array (Fig. 7), more rounded outlines are found, so it appears that the array transistors are particularly tuned to be square-ended. This is not unreasonable, since nearly half the chip is taken up by the SRAM cache memory.
 Figure 8. Plan-view SEM image of Metal 1 in logic area. |
When it comes to the metal levels, at M1 it seems that dual-APSM has been used (double masking as opposed to double patterning). Figure 3 shows the “wiggle” in the VDD line, and Fig. 8 shows an area of standard cells in the logic array, with some very tight Manhattan layout in the cells. It was in these areas that we found the tightest M1 pitch, closer to 150nm than the announced 160nm [1].
With features this densely spaced, and using dry exposure tools, it is obviously a daunting task to define patterns without any faults, even with APSM and the most advanced reticle enhancement and optical proximity correction techniques. Dual APSM takes the hypothesis that phase conflicts can be avoided for both masks, if apertures oriented along the vertical direction are assigned to one mask, and those along the horizontal direction to the other [4]. If Intel is using dual-APSM, I think the hypothesis is proven!
 Figure 9. Plan-view SEM images of M2 (right) and M3 in logic area. |
At M2, we found a very limited use of orthogonal patterning, and M3 none at all; but since the pitch is still 160nm, it is possible that dual masking was used, although the M3 masks would be oriented in the same direction.
 Figure 10. In other parts of the die, Intel has used dummy metal for a much greater proportion of the area, particularly at the M1 level. |
If we look again at Fig. 8, we can see that some of the lines between the logic cells are a darker shade of grey than others in the cells. This is a function of the secondary electrons seen by the SEM detector, but for our purposes it indicates dummy metal lines used in the layout of the part. The same effect is shown (Fig. 9) at M2 and M3. In other parts of the die, Intel has used dummy metal for a much greater proportion of the area, particularly at the M1 level (Fig. 10).
 Figure 11. Improvement in M1 uniformity after Cu etch and CMP enhancements [3]. |
Of course, the use of dummy metal is almost as old as the use of CMP, but this is the first time we have seen it employed so extensively, so densely, and so early in the back-end processing. For CMP control, we usually see small structures such as squares of metal; here, the dummy structures are lines squeezed in at every possible position where there is no active metal needed. However, the regularity of this layout cannot but reduce the lithographic variation, and coupled with CMP improvements (Fig. 11), we get the impressive metallization seen in Figs. 1-3.
 Figure 12. Gate-level image of general logic area. |
We also found the same layout philosophy used at the gate level. Figure 12 is an example of an area of general logic (note that the diffusions are covered by dielectric material in this image). Repetitive columns of metal gate fingers are arranged parallel to columns of M0 trench contacts. In regions where no active devices are required, these metal gate strips serve as dummy structures. Where an active device is required, the column is simply broken, long enough to form a gate finger, and continues on again beyond the device as dummy metal. In the same way, the W trench contacts can be tailored to any length necessary.
This layout has several advantages; in addition to aiding lithography, the use of trench contacts also enables flexibility in choosing where to place a contact up to metal 1. The trenches can be routed to a region over STI to form a contact land, as opposed to being forced to contact the top of a conventional contact stud over active Si. The trench contacts also form butted, or split, contacts, enabling connection of one or several gates to one or several diffusions, without the use of a metal 1 strap. Numerous manufacturers have used butted contacts as a means to reduce the unit 6T SRAM cell size, but the Penryn die marks the first time we have seen Intel use butted contacts to increase packing density in the core logic blocks.
 Figure 13. Performance improvements after dummification [5]. (Intel Developer Forum) |
Intel had mentioned this “dummification” technique in a presentation at their 2006 Developer Forum [5], and in addition to the above advantages, they claim that it reduces leakage (Fig. 13) and improves thermal processing (Fig. 14).
 Figure 14. Process parameter improvement after dummification [3]. |
To monitor the end-of-line results, Intel designers place ring oscillators in all product designs. Performance data such as fmax can be used to identify areas of concern and give a measure of the systematic and random variation seen in the process. Figure 15 shows the trend in fmax over recent process generations. Looking at this, it is apparent even after four generations of shrinkage, variation is amazingly well controlled.
 Figure 15. Trend in systematic within-wafer variation from ring oscillator fmax data [3]. |
In terms of the high-k metal-gate process, Intel has kept its cards close to its chest in recent years, not releasing much information until IEDM. The company has been a little more forthcoming on its DFM efforts, and there has been much commentary about the coming DFM changes at events such as SEMICON, but we had to see an actual chip in order to realize how the design and manufacturing landscape is changing in the transition to 45nm.
However, judging by what we have seen in our Intel analyses, all the work done on improving individual process steps, and the kind of design and layout changes seen above, has paid off admirably in the final product.
References
- K. Mistry et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” Proc IEDM, 2007, pp. 247-250; http://download.intel.com/technology/IEDM2007/HiKMG_paper.pdf; http://download.intel.com/technology/iedm2007/HiKMG_pres.pdf.
- D. James “An Ongoing History of Strain-Now Available with High-k!” WeSRCH paper http://electronics.wesrch.com/Paper/paper_details.php?id=EL1SE1YJ9AKVU&paper_type=pdf&type=%20latest.
- K. Kuhn, “Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS”, Proc. IEDM, 2007, pp. 471-474; http://download.intel.com/technology/IEDM2007/variation.pdf; http://download.intel.com/technology/IEDM2007/variation_pres.pdf.
- D. Bernard et al., “Clear-field Dual Alternating Phase-shift Mask Lithography,” Optical Microlithography XV, Proc. SPIE, Vol. 4691, p. 999-1008.
- S. Rikhi et al., “Design for manufacturing,” IDF 2006, session EPRS008.
DICK JAMES is the senior technology analyst for Chipworks. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, [email protected], www.chipworks.com.
Fun facts about 45nm from Intel
If a house shrunk at the same pace transistors have, you could not see a house without a microscope.
The price of a transistor in one of Intel’s Penryns will be about 1 millionth the average price of a transistor in 1968. If car prices had fallen at the same rate, a new car today would cost about 1 cent.
You could fit more than 2000 45nm transistor gates across the width of a human hair.
You could fit more than 30 million 45nm transistors onto the head of a pin, which measures ~1.5 million nm in dia.
A 45nm transistor can switch on and off approximately 300 billion times a second. A beam of light travels less than a tenth of an inch during the time it takes a 45nm transistor to switch on and off.