Stepper technology enabling wafer-level packaging adoption
03/01/2008
EXECUTIVE OVERVIEW
Driven by the needs for mobile personal electronics, wafer-level packaging (WLP) is now being used for many mainstream ICs. Lithography requirements for WLP must consider overall cost-of-ownership.
Semiconductor assembly and test service houses, packaging foundries, and integrated device manufacturers (IDMs) are increasingly turning to WLP to address the demand for miniaturization, lower cost, enhanced functionality, and higher reliability in today’s personal digital devices.
WLP technology involves packaging ICs at the wafer level instead of the traditional process of assembling the package of each individual die following the dicing process. WLP is a true chip-scale packaging (CSP) technology because the resulting package is nearly the same size as the die. As a result, WLP is viewed as a strategic technology investment by both SAT and IDM companies. Furthermore, WLP paves the way for true integration of device fabrication, packaging, test, and burn-in at the wafer level to enable significant streamlining of the device manufacturing process, from silicon start to device shipment.
Lithography during WLP is one of the final manufacturing steps, so it is critical to eliminate yield losses during these processes. The semiconductor industry moved away from contact proximity aligners for use in front-end-of-line processing-not due to smaller feature sizes, but because of overlay and yield considerations. These considerations also apply to back-end-of-line processing, and are part of the reason for the transition from contact proximity aligners to 1× steppers. However, the main catalyst for the transition from aligners to steppers is the overall cost-of-ownership (COO). Steppers not only eliminate yield loss during lithography processing, but also enable processing of multiple layers on the same reticle, thereby reducing recurring manufacturing costs. Thus, the use of stepper technology enables WLP applications to gain widespread adoption throughout the industry.
WLP market drivers
Historically, the WLP market was driven mainly by small die products. The silicon costs were fairly low because the manufacturer could ensure a large number of die on one wafer. However, the packaging costs continued to increase as the functionality and technology increased in complexity. The transition to WLP enabled an overall reduction in packaging costs for smaller die sizes.
 Figure 1. Cell phone forecast. (Source: Dataquest) |
The cell phone remains the dominant growth driver for this market space (Fig. 1). Recent leading-edge cell phones, for example, incorporate at least a dozen wafer-level packages. As the silicon functionality required for these cell phones increases, the demand for cost-effective and advanced packaging technology has escalated (Fig. 2). According to the Gartner Dataquest market research group, current cell phone market shipments are ~1.08 billion units, and are predicted to grow to ~1.4 billion units by 2010. The sub-segment of smart phones is expected to grow from 140 million units to ~400 million units in the same period. As these newer cell phones come on the market, the need for increased functionality in smaller footprint becomes more critical, thereby accelerating the adoption of WLP technology. While a considerable portion of this work is being done at foundry locations, some IDMs are adding capacity in-house and leveraging WLP technology as a differentiator. We are seeing growth at the device manufacturers, mainly led by analog and RF devices at foundries and companies.
 Figure 2. Wafer-level package for the CSR Bluetooth product. (Source: Tech Search International) |
The use of 1× steppers delivers a high economic value for WLP applications and ensures the best COO for these devices.
Contact Manish Ranjan, director, product marketing, Ultratech Inc., at ph 408/321-8835, e-mail [email protected].