Issue



Emerging materials on the Roadmap for silicon-based IC systems


03/01/2008







EXECUTIVE OVERVIEW

In general, emerging materials will augment silicon transistor technology by providing enhanced speed, lower-power consumption, improved heat dissipation, improved memory capacity/data retention, or added RF/analog functionality while maintaining the large scale integration capability of CMOS. The augmentation of the silicon starting material need not be entirely silicon-based as long as CMOS system improvement is the end goal. As an example, the integration of III-V compound optoelectronics on silicon (Si) for enhanced bandwidth for I/O-limited CMOS technologies would be considered an emerging material application.

The definition of emerging materials is as follows: novel starting materials, structures, and processing methodologies that will enable anticipated roadmap requirements and enhance silicon-based CMOS technology.

The International Technology Roadmap for Semiconductors (ITRS) Emerging Materials Committee has now tracked technologies for close to four years. In that time, some technologies have demonstrated progress towards mainstream applications (i.e., have moved beyond ‘emerging’ status); some technologies have continued to stay active but have not moved into mainstream applications; and some technologies have shown some loss of momentum.

The third column of Table 1 denotes whether actual chip-level products are on the market. For several of the technologies, wafers or starting materials are commercially available (e.g., Ge wafers), but for the scope of our work we consider chip implementation to be the indicator of the technology progression. In a somewhat linked criterion, the fourth column denotes whether the technology is close to mainstream acceptance. Admittedly, this is a somewhat subjective criterion as it is not possible to obtain complete records of how many companies ship how many products with a given technology. From the committee’s discussions, only the use of channel orientation to augment pMOS performance and the use of high resistivity (~1,000 Ω-cm) Si substrates would be considered mainstream technologies at this point. The tracking of high resistivity Si substrates will henceforth be limited to substrates with resistivity >10,000Ω-cm.

Click here to enlarge image

Strained Si-on-insulator (SSOI) and Ge channel transistors have increased in momentum from our perspective due to the greater availability of starting materials and some reported advances in the transistor performance. Isotopically pure Si is the only technology that we considered to have lost significance since 2005.

After consideration of the information presented by industry experts and independent evaluation of the technologies being considered for implementation by the semiconductor industry, we identified four distinct categories of alternative materials solutions that are being examined by the semiconductor industry (the fourth category is new to this year’s analysis, and discussion is included in the full ITRS report at http://public.itrs.net):

  1. Thermal management solutions
    a. Silicon on diamond/silicon on silicon carbide
    b. Silicon on aluminum oxide on silicon
  2. Mobility enhancement solutions
    a. Strained silicon
    b. Germanium/strained germanium channels
    c. III-V compound semiconductor channels
    d. Carbon nanotubes
  3. System-on-chip solutions
    a. High resistivity silicon
    b. Optical interconnection on silicon
  4. Memory solutions
    a. Phase change memory

Thermal management solutions

Due to increased transistor density and enhanced current drive per transistor, the amount of power dissipated in modern circuits can lead directly to thermal management problems that could result in the degradation of circuit performance or reliability. The following subsections address materials solutions that enhance the thermal conductivity of CMOS circuits, thereby mitigating potential hot spots and the overall overheating of circuit components.

Silicon on diamond/silicon on silicon carbide. Materials with better thermal conductivity than Si in the immediate vicinity of the transistors could potentially keep circuits cooler due to their more efficient heat removal. For example, single crystal diamond and single crystal silicon carbide (SiC) have thermal conductivities, 20Wcm-1K-1 and 3-4Wcm-1K-1, respectively, that are much greater than that of 1.5Wcm-1K-1 for Si. Thus, it would be favorable to have diamond and SiC regions incorporated into chip architectures for thermal management reasons.

Combining CMOS-quality Si with either diamond or SiC requires wafer bonding and layer transfer. In the case of diamond, the only reasonable option for the foreseeable future is to use a polycrystalline diamond film (with significantly lower thermal conductivity than equivalent single-crystal layers, but dependent upon the grain size) sandwiched between a Si wafer and a thin Si active layer. Since it is difficult to obtain a smooth surface of polycrystalline diamond, a planarizing layer of polysilicon or SiO2 may have to be used between the Si film and the diamond. The SiO2 layer would also help in passivating electrical defects at the lower Si interface.

Several different configurations with SiC are potentially possible. An oxidized layer of Si can be transferred to either a single crystal or a polycrystalline SiC wafer. Because of the cost considerations, polycrystalline SiC is a more attractive solution. Since our last review of this topic, wafers with a layer of Si on polycrystalline SiC (SopSiC) have been made commercially available at 75 and 100mm dia. for use as substrates for GaN based power devices. Extension of this technology to large wafer diameters suitable for high power/high performance Si devices is proceeding.

Silicon on aluminum oxide on silicon. It is well known that the insulator in SOI structures is normally a thin layer of thermally grown SiO2. A high quality dielectric layer with better thermal properties than SiO2 would be of interest for improving heat dissipation in SOI circuits. Amorphous, polycrystalline, or possibly single crystalline aluminum oxide, Al2O3 (called sapphire when it is single crystalline), has a thermal conductivity 10-30 times higher than SiO2 and would thus improve heat dissipation during SOI circuit operation [1].

Mobility enhancement solutions

Modern transistor technology has essentially reached the limit of the fundamental electronic capabilities of Si. High mobility materials for enhanced transistor speed and reduced power consumption are considered paramount for modern CMOS applications.

Strained silicon on insulator (sSOI). Strained Si technology, the introduction of elastic strain in Si transistor channels, is the most widely accepted method for enhancing the carrier mobility of Si (Table 2). There are two variants to strained Si technology that have been researched and demonstrated: 1) local strain introduction via transistor module engineering and 2) global (wafer-scale) strain introduction via silicon-germanium (SiGe) epitaxial processes (and layer transfer processes for global strain with SOI). For the purposes of this document, local strain introduction techniques are not considered emerging materials since they are already in production.

Click here to enlarge image

Global strained Si technology is based upon the deposition of Si1-xGex alloys, which form a template for subsequent channel layer deposition (and layer transfer process in the case of sSOI). Typically, the alloys have a Ge content in the range of x = 0.15 to 0.30. The deposition of pure Si on such a template results in biaxial (i.e., in the two in-plane directions) strains on the order of 1%. Due to strain introduction at the starting materials stage, global or wafer-scale strained Si is more universal in nature and some of its attributes or specifications can be addressed more generally.

Germanium/strained germanium channels. Transistors with pure Ge channels are being investigated for implementation in next-generation microelectronics. The ultimate advantage of working with Ge is the carrier mobility enhancement, making it attractive for high-speed circuit applications. Low field electron mobility in Ge is more than double that of Si (3900 vs. 1500cm2/V-sec) and the increase is four-fold for holes (1900 vs. 450cm2/V-sec). Despite the intrinsic speed advantages of implementing Ge transistor technology, Ge has not established a strong presence as an electronic material for ubiquitous microelectronic application because it does not form a stable oxide that would be suitable for gate stack formation. However, as the industry is beginning a transition to high-k dielectric films, necessitated by electron tunneling through very thin SiO2, new opportunities are being explored to implement pure Ge transistor technology.

The three embodiments of Ge substrate technology are generally: 1) bulk Ge substrates, 2) Ge layers transferred to oxidized Si handle wafers to form Ge-on-insulator (GeOI), and 3) epitaxial deposition of Ge thin films on Si substrates in various configurations. Bulk Ge substrates (grown via the Czochralski method) are more difficult to make than bulk Si substrates, and the economics of high volume manufacture are still unsure. Ultimately, even if the technical and economical issues were resolved, it is unlikely that the world’s Ge reserves could support the complete replacement of bulk Si substrates with Ge. Therefore, it is expected that technology developments will be aimed at making Ge substrates that are suitable for repeated exfoliation processes in the formation of GeOI. GeOI also reduces the likelihood of excessive Ge junction leakage during device implementation. Epitaxial Ge technology is especially promising, and necessary, for the implementation of biaxially strained Ge channels, which have been shown to have the highest hole mobility.

Since Ge inversion layer mobility is the key metric in comparison to traditional Si transistor technology, the integration of a reliable gate stack is paramount to exploiting the benefits of Ge transistor technology. Germanium oxynitride [2, 3], aluminum oxide [4], hafnium oxide [4], and zirconium oxide [5] high-k dielectrics have been implemented with Ge channel transistors with varying degrees of success. However, no completely satisfactory solution has been demonstrated with Ge channels. This in part has led to less than anticipated mobility enhancements for holes and typically electron mobilities that are inferior to that of Si. For methods that use epitaxial Ge layers, thin layers of Si, which preserve the gate oxide integrity, have been used to cap the Ge channel layers. Relaxed and biaxially strained embodiments of Ge transistors using Si capping layers have markedly better mobility characteristics (2-10×) than Si control transistors [6]. Some questions about properties of Ge in such applications require further analysis. Ge has a smaller bandgap than Si, which can cause junction leakage problems. However, it has been reported that in the presence of significant strain, Si may experience more leakage than Ge [7]. Lastly, the saturated high field drift velocity of charge carriers in Ge is somewhat lower than that of Si. Recent experiments and simulations are helping to fully define the benefits and trade-offs of modern Ge electronics [8].


Electron and hole mobility anisotropy for silicon [9].
Click here to enlarge image

Surface orientation. Another approach to improve on the mobility and current drive capabilities of Si involves the exploitation of the mobility anisotropy of Si. The figure on p. 46 shows the mobility of electrons and holes for different surface orientations and in the case of the (110) surface, two different in-plane channel directions. It is well known that electron mobility is highest for the traditional Si substrate/transistor configuration, which includes a (100) surface with a <110> channel direction, while hole mobility is highest for a (110) surface with a <110> channel direction. A hybrid substrate configuration [9] has been proposed to allow for the ultimate mobility configuration for each carrier. As with conventional Si surface and channel geometries, the introduction of strain in tandem with different substrate orientations has also been investigated [10, 11].

Carbon nanotubes

Carbon nanotubes (CNT) have remarkable physical and chemical properties. CNTs, only 1-2 nm in diameter, have a tensile strength that is 375 times greater than that of steel. In addition, the Young’s modulus and thermal conductivity of CNTs are nearly those of diamond. The density of a hexagonal array of CNTs is about 1.4 g/cm3. This combination of properties leads to a wide variety of potential applications. Single-walled carbon nanotubes (SWCNT) are attractive for extreme scaling of integrated circuits due to their small diameters (~1nm), long lengths (~100µm), and thermal stabilities. A SWCNT can be either semiconducting or metallic, and electrical properties depend on the tube’s longitudinal axis relative to principal axes of a graphene sheet (helicity) [12] and its diameter. SWCNTs are being considered for application as transistors, diodes, and interconnects in future integrated circuits, though difficult processing problems remain to be solved before widespread use is realized.

CNT transistors. CNT field effect transistors (CNTFET) can be modified and controlled in many of the same ways that Si MOSFETs can be tailored. They can be p-type or n-type and their threshold voltages can be set by doping. CNTFETs can exhibit bulk-switched behavior like MOSFETs with characteristics equal to or superior to conventional Si devices. The advantages of CNTFETs include high mobility, no mobility degradation when integrated with high-k dielectrics, ballistic transport, adjustable band gap, and low contact resistance. Integration of CNTFETs has also been shown viable through demonstration of several kinds of small circuits with CNTFETs including NOT and NOR logic gates, flip-flops, ring oscillators, and voltage inverters.

FETs utilizing CNTs as channel materials are one-dimensional (1D) devices due to the small diameters of CNTs. The 1D nature of CNTFETs draws performance comparisons to Si nanowire FETs, which have been shown to have superior scalability over even double-gate FETs in simulations [13]. CNTs may be ~5× thinner than Si nanowires leading to improved scalability, since Si carrier mobility degrades as the Si becomes thin [14] whereas this is not the case for CNTFETs, which have hole mobilities up to 80 times higher and lower self-heating than that in Si nanowires with comparable dimensions [15, 16]. CNTs also have atomically smooth surfaces for hundreds of micrometers and all the carbon bonds are within the CNT, reducing electronic states at the interface with the gate dielectric. These features allow for ballistic transport and higher on-currents than Si nanowires [15-17].

Transistors using CNTs as channels do not offer any advantages over other materials at the quantum mechanical tunneling limit between the source and the drain. This limit is predicted to be at a gate length of about 5nm, but up to this limit CNTFETs can offer improved performance over Si MOSFETs.

Metallic CNTs. Metallic SWCNTs have better conducting properties than copper and can carry very high current densities (1000× higher than copper), making them attractive for highly scaled interconnects. Calculations for the 45nm technology node show no performance enhancement for CNTs over similarly sized copper lines. However, the performance enhancement is expected to be 30-80% for the 22nm node, depending on the mean free path of electrons in the CNTs [18, 19]. Multi-walled CNTs in a 20nm dia., 150nm long via have demonstrated a resistance of 8 kΩ and a current density of 500MA/cm2 [20]. While these values are about an order of magnitude lower than ideal, the work demonstrates feasibility of the use of CNTs as interconnects.

III-V channel transistors

High mobility channel materials that are compatible with Si are being sought as one way to extend the performance of integrated circuits beyond the physical limitations of Si based electronics. High mobilities can offer comparable or improved performance at lower voltages than standard Si, providing increased power saving. In addition to strained Si, and CNTs described above, III-V materials offer interesting possibilities and significant challenges as channel materials. Many III-V materials offer very high electron mobilities, as high as 3-50× that of Si. Examples include materials such as GaAs, GaSb, and InSb. There is a relatively short list of materials that offer high hole mobilities. While GaSb and InSb offer modest improvements in hole mobility over Si, Group IV elements such as C and Ge may also need to be integrated as channel materials for PFETs to maximize performance scaling.

Much of the processing to make devices with the III-V materials is known. High electron mobility transistors (HEMT) made with III-V compound materials have been implemented commercially for very high frequency applications for a very long time. However, scaling of such devices was limited to gate lengths above 100nm. Recently, HEMTs with gate lengths as short as 50nm with high Ion/Ioff ratios have been produced [21]. The band gap of materials generally decreases as their mobility increases. Thus, voltage scaling will have to continue in order to take advantage of high mobility materials.

While these materials show significant promise, there are also significant challenges associated with their implementation. Any new material destined to replace or enhance CMOS integrated circuits must ultimately integrate well with Si. The most promising materials have lattice constants significantly different from that of Si. Hence epitaxial films must be engineered well to enable new, high-mobility channel materials. Another challenge is that the density of states for many high mobility materials is low, limiting the amount of current they can support.

Improving the ability to dope the source-drain regions of such materials will be key to reducing parasitic resistances external to the channel. High-k gate dielectrics, just now about to be introduced with high volume Si integrated circuits, will be needed to minimize gate leakage and further gate length scaling for III-V compound channel materials. Recently, researchers built and demonstrated enhancement-mode, high-mobility, NMOS devices incorporating a high-k gate dielectric on a GaAs channel without Fermi pinning [22].

System-on-chip solutions

As core digital logic continues to advance in terms of performance, there is an increasing need to further state-of-the-art chip capabilities in other areas, such as input/output functions and integration of more functionality.

High resistivity silicon. Material and device developments over the past few years have enabled the production of CMOS and BiCMOS transistors capable of operating at very high RF frequencies. The fabrication sequence of such devices is compatible with standard digital CMOS processing, allowing the monolithic integration of RF circuitry with high-speed logic and memory. This has led to the emergence of whole new classes of mixed digital/analog devices with wireless communication capabilities.

Most CMOS logic and memory circuits today are fabricated on bulk wafers with resistivity in the range of about 1-20Ω-cm, or epi wafers with a similar epi resistivity on a heavily doped substrate. SOI wafers are also used for both CMOS and BiCMOS devices. The integration of RF circuits into CMOS devices favors a shift to a very high substrate resistivity. This is because, unlike digital CMOS, RF circuitry requires linear, analog devices with low noise and precision passive components. Very high substrate resistivity decreases capacitively-coupled cross-talk between digital, analog, and RF components, improving noise isolation. It also improves the quality factor of spiral inductors by decreasing eddy current losses, and improves the quality factor of metal-insulator-metal (MIM) capacitors by decreasing parasitic substrate capacitance.

The intrinsic resistivity of Si, ~725,000Ω-cm at room temperature, is the maximum resistivity theoretically attainable. In practice, resistivity greater than 50Ω-cm offers tangible benefits to device performance. “High resistivity” is typically defined as resistivity ≥ ~1000Ω-cm, but as we noted in the introduction, we can consider ~1000Ω-cm resistivity substrates to be mainstream. However, much higher resistivity (~10,000Ω-cm) Si substrates are still being sought and fall into the category of emerging materials.

Czochralski (CZ) growth is preferable to Float zone (FZ) for large-scale production of large diameter wafers; however, the use of a silica crucible in CZ growth leads to two problems. First, boron is a low-level contaminant in SiO2 that is very difficult to remove. Thus, unintentional boron contamination of CZ Si from even the highest purity crucibles makes it very difficult to produce substrates with resistivity > ~5000Ω-cm. Secondly, the crucible introduces interstitial oxygen into the CZ Si, leading to potential thermal donor formation problems. CZ growth methods exist that can reduce Oi to a level where thermal donor generation is insignificant, but as in the FZ case, these low-Oi wafers do not develop the oxygen precipitation necessary to produce internal gettering nor strengthen the wafer.

Currently, the most promising approach to suppression of thermal donor formation at the higher Oi levels found in standard CZ Si is to deliberately grow oxygen precipitates in the wafer to consume interstitial oxygen [23, 24] while still maintaining control of the requisite wafer warpage. Growth of a high density of large precipitates can consume enough of the interstitial oxygen to minimize subsequent thermal donor formation. As an added benefit, the oxygen precipitates provide internal gettering in the wafer. The oxygen precipitation heat treatment can be lengthy however, adding to the wafer manufacturing cost. The growth of large precipitates and concomitant decrease of Oi also lower the yield stress of the wafer. Very high temperature heat treatments (T>1100-1200°C) in the fab can also re-dissolve some of the precipitated oxygen, increasing Oi and leading to thermal donor formation again, during subsequent thermal processing. Efforts continue to develop a robust and cost-effective manufacturing process that can control thermal donor formation while providing acceptable internal gettering in high resistivity, CZ Si.

The effects of co-doping CZ material with suitable deep level traps have also been investigated. The decreased resistivity due to background boron concentration on CZ wafers could be counteracted by using suitable doping species [25, 26]. It is not clear at this time if co-doped material is compatible with device processing requirements.

Integrated optoelectronics on silicon. Monolithic Si has become the mainstay of the digital computing industry due to its unique integration capabilities and efficient cost structure. Despite Si’s prowess in most mainstream semiconductor applications, a need is developing to introduce technologies compatible with Si that enable high speed, optical communications for application within chip, chip-to-chip, and beyond. Techniques akin to packaging (e.g., hybrid chip mounting) administer to some of this need, but monolithic integration of light emission, light detection, and light routing capabilities with Si CMOS computing provides the greatest potential for Si microsystem enhancement.

In general, light emission and light detection offer the greatest challenges when considering optoelectronic integration with Si CMOS because of Si’s limited utility in such applications due to its indirect band gap. Recently, a continuous-wave Raman Si laser has been demonstrated [27]. There are two other broad approaches for the integration of light emission and light detection communications capability with Si: 1) alter the Si microstructure to induce a corresponding change in its energy band diagram that would enable efficient light coupling and conversion, and 2) work with interlayer approaches to introduce high quality photonic materials (e.g., III-V compounds, Ge photodetector layers, or carbon nanotubes) on the Si substrate.

Conclusion

An exhaustive treatment of alternative memory technologies is considered in the Emerging Research Devices section of the ITRS, while the Emerging Materials section provides some supplemental information on phase change memory technology.

All of the assessments in this article are a snapshot of what the ITRS Emerging Materials Committee believes at the present time. In the future, it is anticipated that commercial trends and technological progress will alter our analysis. We welcome input from the semiconductor community. Thoughts can be sent to the committee chairman, this author.

Acknowledments

In 2003, the ITRS Starting Materials sub-Technology Working Group established the Emerging Materials Committee to examine and track alternative materials technologies that are under consideration for implementation in conjunction with traditional CMOS scaling. This document, which was released in 2007 and can be found at http://public.itrs.net, is the second full revision of the original 2003 document.

The committee is grateful to the following industry experts who presented information on several relevant topics: Steve Hudgens, Ovonyx, on phase change memory; Sajan Saini, MIT Microphotonics Center, on microphotonics; Don Scansen, Semiconductor Insights, on cutting-edge CMOS; Vahé Mamikunian, Lux Research, on emerging nanotechnology; and Ravi Kanjolia, Epichem, on CVD/ALD chemistry.

References

  1. C. de Beaumont, et al., Silicon-on-Insulator Technology and Devices XII, ECS Proc., Vol. 2005-03, edited by G. K. Celler, et al., p 231, 2005.
  2. Chui, et al., IEEE Electron Device Lett., 25, p. 613, 2004.
  3. Shang, et al., IEDM Tech. Dig., p. 441, 2002.
  4. Chen, et al., IEEE Trans. Electron Devices, 51, p. 1441, 2004.
  5. Chui, et al., IEDM Tech. Dig., p. 437, 2002.
  6. Lee, et al., IEDM Tech. Dig., p. 429, 2003.
  7. Krishnamohan, et al., IEDM Tech. Dig., p. 937, 2006.
  8. Saraswat, et al., IEDM Tech. Dig., p. 659, 2006.
  9. M. Yang, et al., IEDM Tech. Dig., p. 453, 2003.
  10. T. Mizuno, et al., IEEE Electron Device Lett., 24, p. 266, 2003.
  11. T. Mizuno, et al., IEDM Tech. Dig., p. 809, 2003.
  12. J. Wilder, et al., Nature, 91, p. 59, 1998.
  13. J. Wang, et al., IEDM Tech. Dig., p. 695, 2003.
  14. K. Uchida, et al., IEDM Tech. Dig., p. 47, 2002.
  15. T. Durkop, et al., Nano Lett., 4, p. 35, 2004.

  1. S. J. Wind, et al., Phys. Rev. Lett., p. 0583011-4, 2004.
  2. J. Guo, et al., IEDM Tech. Dig., p. 703, 2004.
  3. A. Naeemi, et al., Electr. Dev. Lett., 26, p. 84, 2005.
  4. A. Naeemi, et al., IEDM Tech. Dig., p. 699, 2005.
  5. F. Kreupl, et al., IEDM Tech. Dig., p. 683, 2004.
  6. J. del Alamo and D.-H. Kim, IPRM, p. 51, 2007.
  7. K. Rajagopalan, et al., IEEE Electron Device Lett., 28, p. 100, 2007.
  8. T. Abe and W. Qu, ECS PV 2000-17, 491-500, 2000.
  9. Ohguro, et al., Symposium on VLSI Technology, 2002, 158-159, 2002.
  10. Mallik, et al., Semiconductor Science and Technology, Vol. 18, No. 6, pp. 517-524, 2003.
  11. Mallik, et al., Proceedings of the 36th European Solid States Device Research Conference, pp. 435-438, 2006.
  12. H. Rong, et al., Nature, 433, p. 725, 2005.

Mayank Bulsara received his MS and PhD in materials science and engineering from MIT. He chairs the ITRS Emerging Materials Committee. He is also president of Atlas Technology Corp., a consulting firm focused on evaluation and development of emerging semiconductor technologies. Contact him at e-mail [email protected].