Damage-free cleaning and inspection of advanced multiple-gate FETs
03/01/2008
EXECUTIVE OVERVIEW
Multiple-gate FETs incorporating narrow silicon fins have been investigated as an alternate to traditional CMOS technology. For silicon fins to be manufactured in high-volume fabs, new processes will be needed, and established cleaning and inspection tools can be used for these new processes. Cleaning tools based more on physical instead of chemical mechanisms-such as cryogenic aerosols, megasonic immersion, and liquid sprays-have been shown to remove particles without damaging fins. Inspection using bright-field i-line spectral imaging provides the highest defect-of-interest capture rate for 32nm technology generation device structures.
Advanced transistor structures, such as the multiple-gate field effect transistor (MuGFET), offer improved short channel effects (SCE) control compared to the bulk-Si MOSFET [1]. Hence, they may be adopted in CMOS technology as early as the 32nm technology generation [2]. In MuGFET structures, the current conduction is on the sidewalls of silicon fins. Thus, tall fins are desirable for high drive current per unit footprint. At the same time, SCE control requires narrow fin widths. Therefore, for the 32nm technology generation, silicon fin width is expected to be ~15nm, while silicon fin height will be ~50nm. Such tall and narrow features present unique challenges to cleaning and defect inspection, which must be addressed before MuGFETs can be introduced into a manufacturing environment.
We have demonstrated that available technologies have the ability to inspect with a high defect-of-interest capture rate and to clean the silicon fins without damage. Pre- and post-inspections indicate no damage to the silicon fins for each of the three cleaning technologies studied.
Experimental
Silicon fins were patterned on silicon-on-insulator (SOI) wafers with 193nm lithography and reactive ion etch (RIE) trimming. The 35 die on the 200mm wafers were each patterned with a series of silicon fins of varying lengths. The fin lengths varied from the shortest of 0.29µm up to the longest of 100µm. The fin arrays were either anchored by source and drain pads or free standing. Figure 1 shows examples of both fin types.
 Figure 1. SEM images of MuGFET structures. Silicon fins are either a) anchored by source and drain pads or b) unanchored and free standing. |
Silicon fin lengths of 0.5µm are likely to be used for device manufacturing at the 32nm technology generation. Figure 2 contains a TEM of the silicon fin under study, confirming the width and height are also consistent with the 32nm technology generation.
 Figure 2. Cross section TEM image of the MuGFET silicon fin. Silicon fin width is ~20nm and the height is ~50nm. |
Automated inspection was performed on the 200mm SOI wafers using a KLA-Tencor 2365 high resolution imaging inspection system. I-line, bright-field spectral imaging provided the highest defect-of-interest capture rate. SEM inspection of defects present before cleaning provided verification that process defects were mostly of two types; regions of non-uniform fins, or thin silicon fins. Figure 3 shows examples of defects from the silicon fin fabrication process.
 Figure 3. SEM images of defects present before cleaning include a) regions of non-uniform fins, and b) thin silicon fin. |
Damage-free cleaning of MuGFET structures has been evaluated with three technologies at FSI International. Two of the cleaning technologies-the single wafer spray and advanced batch megasonic-are wet cleaning techniques, while the third-cryogenic aerosol-is a dry technique. The common feature of these cleaning technologies is they apply a force to the wafer surface that can be tuned to maximize defect density reduction without introducing feature damage. One process parameter was varied for each of the three cleaning technologies. The attributes of each cleaning technology will be discussed first, followed by the silicon fin process results.
Fin cleaning technologies
The dry cleaning technology uses momentum transfer of cryogenic aerosol clusters to dislodge and remove contaminants [3]. The cryogenic aerosol is generated from either a combination of argon and nitrogen, or nitrogen only. In this work, the aerosol is formed when a cryogenically cooled mixture of gas and liquid nitrogen is dispensed through a nozzle with a series of orifices located above the substrate [4, 5]. The resulting liquid droplets solidify to solid aerosol clusters before contacting the wafer surface. This method does not cause any material loss or charging of the substrate. During processing, the chamber is held at a reduced pressure to enhance the aerosol formation process. At lower chamber pressures, the cryogenic aerosol will have higher energy. Chamber pressures of 50 and 30Torr were investigated. Figure 4 schematically depicts the detachment of contamination by momentum transfer from the cryogenic aerosol. Thermophoresis and a laminar flow of nitrogen carry the contaminant away from the wafer surface after detachment.
 Figure 4. The solid cryogenic aerosol cluster detaches a contaminant from the wafer surface. |
The second cleaning technology, an immersion cleaning system, is equipped with a megasonic acoustic diffuser. While the application of megasonic energy in batch systems is an established cleaning technique for silicon wafers, it has been removed from processing sensitive gate structures with features smaller than 130nm [6]. Incorporating an acoustic diffuser improves the megasonic field uniformity and presents the opportunity to reintroduce megasonic agitation into the process flow [5, 7]. Regions of high megasonic intensity that are typically characteristic of batch megasonic systems are eliminated in this configuration. Figure 5 compares a megasonic tank with and without the acoustic diffuser. As can be seen, the megasonic, and therefore the cavitation uniformity, is improved as a result of eliminating the high sound intensity regions. The overall level of sound intensity in the tank can be controlled by the megasonic input power, and this is the parameter that was varied.
The third system evaluated uses a single-wafer spray system. Liquid exiting an orifice is atomized by a flow of gas to form liquid droplets. The liquid droplets impinge on the wafer surface and spread out to form a localized area of high velocity flow [8]. The contaminants are removed by direct contact with the liquid droplets or by entrainment in the high velocity flow as the droplet deforms on the wafer surface. By varying the atomization gas flow, the removal force of the liquid droplets can be varied. Two different conditions were evaluated for each cleaning technology as listed in the table on p. 50. Included in the table are the blanket particle removal efficiency (PRE) results, and a description of the silicon fins that were damaged for the six type-I and three type-II SOI wafers investigated.
Cleaning results
The results confirmed the ability to clean the silicon fins without damage. For all of the processing conditions investigated, damage was very low and isolated to small lengths (<300nm) of the silicon fins. There appears to be inconsistent damage results between the SOI type-I and type-II wafers for cleans using either the cryogenic aerosol or immersion systems. This may be related to the contact area between the silicon fins and the underlying oxide. The silicon fins are exposed to HF after their formation, which can result in an undercut of the oxide at the silicon fin/oxide interface. This oxide undercut will vary with the quality of the oxide used for the type-I and type-II SOI.
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The only silicon fins that were damaged were greater than 10µm in length, as listed in the table. The projected length of the silicon fins suitable for the 32nm technology generation is 0.5µm. Silicon fins of this length were not damaged by any of the processing conditions investigated. The damage-free results also indicate the silicon fins are more robust than polysilicon of similar feature sizes.
Previous work on 45nm polysilicon structures with the cryogenic aerosol has shown the ability to process without damage at 50Torr chamber pressure, but the more aggressive aerosol at 30Torr chamber pressure did show damage. The reason for the ability to process the silicon fins with more aggressive process parameters without damage is believed to be for two reasons. The first is the presence of source and drain pads anchoring the fins. The second is the interface between a single crystal silicon fin and a thermal oxide is more robust than a polysilicon and gate oxide interface [9].
If this type of architecture is adopted for MuGFET structures, cleaning technologies incorporating uniform removal energies may be able to provide the solution to the tightening material loss outlined for the advanced technology generations in the International Technology Roadmap for Semiconductors (ITRS) [10]. It may be possible to use less chemical etching for cleaning of these structures due to the ability to incorporate removal energy such as momentum transfer and cavitation.
Summary
- The results have shown the silicon fins proposed for MuGFET structures can be inspected with a high defect of interest capture rate and processed with current energetic cleaning technologies without damage. While it is not known which type of gate architecture will be adopted at the 32nm technology generation, application of energetic cleaning technologies appears to be possible with the silicon fins in this work. This would aid in meeting the material loss requirements as outlined in the ITRS while maintaining a high level of damage-free, defect removal.
Acknowledgments
The authors would like to thank Kara Sherman (formerly with KLA-Tencor), Hucheng Lee of KLA-Tencor and Klaus Schruefer of Infineon Technologies for their efforts with this work. This paper first appeared in Solid State Phenomena, Vol. 134, 2008, pp. 213-216, Proceedings of Ultra Clean Processing of Semiconductor Surfaces VIII.
References
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Jeffrey M. Lauerhaas received his BS in chemistry from the U. of Wisconsin at Oshkosh, and his masters and PhD in chemistry from the U. of California at San Diego. He is a member of the technical staff at FSI International, 3455 Lyman Blvd., Chaska, MN, USA; ph 952/361-7928; e-mail [email protected].
Rinn Cleavelin earned his masters and PhD from Texas Tech U. He retired as a Distinguished Member of the Technical Staff at TI and is now an independent consultant.
Weize Xiong -As of press time, no information was available.
Koki Mochizuki received his PhD from the U. of Texas at Austin. He is a senior staff process engineer at Lam Research.
Brian Clappin received his masters in engineering and his MBA from San Jose State U. He is a senior applications engineer at KLA-Tencor, e-mail [email protected].
Thomas Schulz received the Dipl.-Ing. and Dr.-Ing. in electrical engineering from the Ruhr-University Bochum, Germany. He has worked on device development projects at IMEC in Leuven as a senior staff engineer of Infineon Technologies Leuven.