High efficiency solar cells with printed Al-alloyed rear contacts
03/01/2008
EXECUTIVE OVERVIEW
Processes have been developed to create n-type silicon cells on thin wafers with screen printed aluminum-alloyed rear junctions. An independently confirmed record-high efficiency of 17.4% (140cm²) has been achieved on floatzone silicon wafers using simple and low cost fabrication techniques. Moreover, model calculations allow us to identify the potential for further enhancement of the cell efficiency towards 18.0% by improving front surface passivation. After some optimization, high efficiencies may be conceivable on n-type multi- crystalline substrates as well.
The vast majority of today’s commercial silicon solar cells are made from p-type doped material. More than 80% of the produced solar cells have a homogeneous emitter, a PECVD-SiN layer as antireflective coating, and screen printed contacts on both sides. For the backside, an aluminum paste is used to create a back surface field during the contact co-firing.
Recently, n-type silicon materials have received much interest as they are considered promising candidates for future generations of high-efficiency solar cells. This interest is based on several developments and findings:
- High carrier lifetimes in n-type multicrystalline (mc) wafers, often significantly higher than in p-type wafers.
- Theoretical and experimental evidence for less recombination-active defects in n-type silicon [1].
- Tolerance of n-type silicon to high temperature processing with respect to p-type silicon [2].
- Shortage of silicon feedstock for the PV industry, and an unused potential supply of n-type silicon waste.
- New materials (ribbons, metallurgical feedstock) for which the above aspects favor n-type doping.
- Need for technology development toward very thin wafers and high cell efficiency, for which n-type silicon based solar cells may have advantages.
However, in spite of these advantages, n-type solar cells are not yet abundantly used in industry. To be useful, n-type silicon solar cells must have stable efficiencies of at least the same level as for p-type. A few solar cell concepts based on n-type Si materials are currently under investigation. One of these concepts is the Al-alloyed back-junction cell [3-10]. This concept was introduced for the first time by EBARA Solar Inc. in 2000 [9], and it represents a fast way for industry to move from p-type to n-type substrates because of the possibility of maintaining the same process sequence. The only differences, as compared with the conventional p-type (n+pp+) process, are that during the phosphorus diffusion a front surface field is created instead of an emitter, and during the contact co-firing the aluminium back junction is formed.
Triggered by an increase in costs, wafer thickness in the industry is decreasing rapidly and it is becoming more important to develop all rear contacted solar cell processes. Aluminum rear-junction is an interesting and elegant approach to study and identify the material limitation for developing all back-contacted solar cells. In particular, this concept can be well used to study limitations of mc n-type substrates for high efficiency rear-emitter cells.
Recently, cell efficiencies up to 17.0% were reported for Al-alloyed rear junction cells [7]. Our n-type cell development is based on the Al back-junction, and we independently confirm new record-high efficiency of 17.4%. We present modeling showing possibilities and limitations for further improvements, and also focus on mc-Si n-type wafers for high-efficiency rear-junction application.
Experimental procedure
The cell process is developed on 148.5cm2 Float Zone (FZ) n-type monocrystalline silicon wafers, but we also have preliminary results on 156.25cm2 industrial n-type mc-Si silicon wafers. The cell process we used is based on in-line processing for diffusion, co-firing, and on process steps which can be industrialized. The rear junction as well as the front surface field (FSF), anti-reflection coating (ARC), and the metallization are comparable to an industrial standard n+pp+ process. Figure 1 shows the basic process flow and a schematic cross section of the Al back junction cell.
 Figure 1. a) Process flow chart and b) the schematic cross-section of the standard back junction cell. |
It starts by a texture (isotexture or random pyramids) etch of the surface. Then the front-surface field is formed by phosphorus diffusion in an infrared conveyor belt furnace from a spin-on source, resulting in 55-70Ω/sq. front surface field. Subsequently, rear side polishing etch is carried out followed by the phosphorus glass removal and the PECVD SiNx ARC deposition on the front side. This process sequence does not require further wafer dicing or other methods for junction isolation, and thus the entire initial wafer area is used.
The silver grid is then screen-printed on the SiNx front side, followed by screen-printing of Al on the whole rear side of the cell. Both contacts are co-fired in an infrared conveyor belt furnace, thus also forming the p+ junction at the rear.
Cell results
The table summarizes the solar cell parameters of the best results obtained for mc-Si and FZ substrates. The highest efficiency is obtained for high substrate resistivity. This is in agreement with model calculations [4, 8], which show that, in order to benefit from the full potential of this type of solar cell, the wafer resistivity should be higher than 10Ωcm (with a thickness of less than 200µm). The thicknesses of the solar cells presented in the table are typically between 165-185µm. On the other hand, it is important to know what limits the efficiency at lower substrate resistivity, especially for mc-Si substrates.
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To understand this, we first investigated the internal quantum efficiency (IQE) of the cells shown in the upper part of the table (above the dashed line). These cells have been fabricated in the same run and have received our industrial standard phosphorous FSF diffusion of 55-63 Ω/sq. Figure 2 shows the experimental IQE (symbols) together with the PC1D fit (lines) using a measured front doping profile and surface reflection (Fig. 3), and assuming a constant Al doping profile for the rear junction.
The relevant fit parameters for the modeling are the bulk lifetime and the front surface recombination velocity (SRV). Since for monocrystalline wafers the bulk lifetime is very high (>1ms), it does not limit the IQE in the lower wavelengths regime, which is completely determined by the SRV. The fit to experimental data reveals a SRV of 6.0(±1) × 105cm/sec for both FZ wafers with resistivity of 3.8 and 30Ωcm, respectively.
 Figure 3. Measured front surface reflectance of isotexture and random pyramids etched surfaces-with and without SiNx antireflection coating layer on top. |
Hence, the difference observed in IQE or in power conversion efficiency between these wafers is accounted only by the difference in their substrate resistivity. Such a good agreement between calculated and experimental data indicates SRV is the limiting parameter for solar cell efficiency based on monocrystalline substrates having similar Al rear junctions.
The bulk lifetime must be taken into account, however, when we analyze the current-voltage or IQE data of the solar cells fabricated on mc-Si wafers. The IQE fit of the mc cell from the table reveals the same SRV value as that obtained for monocrystalline cells above (6.0×105cm/sec), but with a considerable lower bulk lifetime of only 28 msec (as obtained from PC1D fit).
It has been shown that the ratio of diffusion length and substrate thickness (Ld/d) must be higher than 2.5 to ensure that the cell performance is not limited by the wafer quality [11]. Thus, to meet these conditions, the effective lifetime of the mc substrates must be higher than 130µsec. Hence, besides resistivity, the bulk lifetime is another important factor that limits the efficiency of n-type multicrystalline silicon solar cells with a rear side emitter.
Currently, we are investigating ways to reduce SRV of these types of cells and, thus, to further improve their efficiency. The bottom two rows of the table show the best results of this effort for cells fabricated on FZ wafers. Achieved are ~12mV higher Voc and up to 1.4% higher FF by engineering our phosphorous FSF diffusion and improving our cell process. As a result of this new process, the SRV was further reduced to 1.0(±1.0) ×105cm/sec (by fitting the IQE data).
Furthermore, to explore the full potential of our improved cell process, we have fabricated solar cells having a random pyramids texture etch surface. The conversion efficiency reached in this case is 17.4%, independently confirmed at Fraunhofer ISE CalLab, Freiburg, Germany. To our knowledge, this is the highest efficiency obtained for n-type silicon solar cells featuring a screen-printed aluminium rear-emitter, and it even outperforms the results obtained on p-type (n+pp+) monocrystalline substrates fabricated in a similar way in our lab (data not shown).
Figure 4 shows the model calculations for Voc as a function of SRV. The SRV has been determined from the PC1D fit of the IQE data (as shown in Fig. 2). As demonstrated by the model calculation, the gain in Voc of the cell is indeed due to a lower SRV as a result of our improved phosphorous FSF diffusion. Moreover, the Voc of 633mV is among the highest measured on large area (148.5cm2) solar cells featuring screen printed contacts, and is already close to the Voc limit (about 642mV) of an Al-alloyed rear full area emitter cell [10, 12].
Figure 5 shows the model calculation for the conversion efficiency versus SRV. The starting point of this calculation was the experimental data of the 17.4% efficiency cell (see table). It is clear from the figure that efficiencies of approximately 18% can be obtained even after fully minimizing SRV. With the FF reaching 79%, there are two major factors left that limit the efficiency of this state-of-the-art industrial screen-printed aluminum rear-emitter cell to only 18%. First is the limitation in Jsc due to metallization shading of the front surface (which amounts to 8.0% in our cells), and second is the fundamental limitation imposed to Voc (and Jsc) of only ~642mV, due to recombination that occurs in the Al-alloyed emitter.
Cuevas et al. have reported that the recombination current density in the p+ region formed by screen printed aluminum and alloying cannot be lower than ~500fA/cm2. Such recombination can dramatically limit the Jsc and Voc of a cell even if SRV is minimized and high quality wafers are used [10, 12]. Work is underway to further improve the efficiency of cells towards 18%. It is expected that 130µsec lifetime, which has been measured already, is good enough to reach high efficiencies on mc substrates.
Conclusion
We have demonstrated that a low cost process of fabricating n-type solar cells based on the aluminum rear-emitter concept leads to a new record efficiency of 17.4% for large area (140cm2) monocrystalline FZ substrates. Moreover, by improving the front surface passivation, higher efficiencies could still be realized, as demonstrated by our model calculations. High efficiencies may also be conceivable on n-type multicrystalline substrates after material optimizations such as higher resistivity, increased lifetime, and improved homogeneity.
Acknowledgments
The authors would like to thank all ECN colleagues as well as to Radovan Kopecek and Thomas Buck for cooperation and stimulating discussions, and Ingo Röver and Karsten Wambach for cooperation and providing mc-Si wafers. This work was supported by SenterNovem as project no. 2020-04-11-11-001. The investigated mc-Si wafers were produced in the EC NESSI project, contract ENK6-CT-2002-00660. This paper was first presented at the 22nd European Photovoltaic Solar Energy Conference, September 3-7, 2007, Milan, Italy (proceedings available at www.photovoltaic-conference.com).
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Valentin D. Mihailetchi received his PhD in 2005 from the U. of Groningen, The Netherlands. He is a research scientist at ECN Solar Energy, PO Box 1, 1755 ZG Petten, The Netherlands; ph 31/224-564564, e-mail [email protected].
Desislava S. Sainova received her PhD in 2001 from the U. of Potsdam, Germany. She joined ECN Solar Energy in 2007 as a research scientist on crystalline silicon p- and n-type solar cell processes.
Arthur Weeber studied physics and chemical engineering at the U. of Amsterdam, The Netherlands. After finishing his PhD in 1988 at the same university, he started to work at ECN, where he is now one of the managers of the Silicon Photovoltaics group.
Lambert (Bart) J. Geerligs received his PhD degree in 1990 from Delft U. of Technology, The Netherlands. In 2000, he joined ECN Solar Energy as a research scientist.