Technology news
02/01/2008
Litho workshop: 193nm/DEDE for 32nm, weighing 22nm options
Immersion lithography was the central theme at the 2007 (formerly IEEE) Lithography Workshop (Dec. 9-13, Puerto Rico)-literally. For the first time in 50 years a tropical storm hit after the hurricane season, soaking attendees trying to relax under the palm trees of the Rio Del Mar Resort.
Intel has started production at the 45nm node, with other chipmakers in-step or close behind. Surprisingly, Intel used an all dry processes for their 45nm node. They also used double patterning to create one layer (the gate layer).
With the 45nm node in production, this conference turned its attention to the 32nm and 22nm nodes. As one speaker observed, “Unfortunately, this time we know what our lithography tool will be: 193[nm] immersion.” EUV is not ready, so 193nm immersion tools must be stretched to make circuit patterns at the 32nm node.
Though it looked very carefully at inverse lithography, Intel has decided to use 193nm immersion and double patterning for the 32nm node. Speakers from nearly all the major IC companies reported the same general plan, but the details remain to be determined.
There will be many forms of double patterning, and each kind of chip (flash, DRAM, or logic) will probably have its own flavor. Spacer techniques can double the pitch, but asymmetrical spacer process errors generate image placement errors, and the spacer process appears to be overly complex. Double exposure, double etch (DEDE) has the disadvantage that overlay errors cause CD errors, but the processes are known.
To save some of the cost of DEDE, a lot of work is going into “freezing” the first pattern in resist, then imaging the second pattern, then etching the combined result. There are concerns about production cycle times, and there is a strong desire to keep the wafers in the photo-bay. This “freezing” technique clearly needs more work, but if litho toolmakers and maskmakers can hit the overlay tolerances, DEDE looks like the most likely process for the 32nm node.
Design tools are being developed to separate IC layouts into two complimentary mask patterns. Not all layouts can be automatically converted; some manual resolution of conflicts is required. The problem is similar to one encountered a few years ago when “hard” phase shift masks were introduced. There are new design check and simulation challenges, and it is clear that many IC houses now do full-chip simulation to find and alter “hot spots” in their designs-one paper at the IEEE litho workshop described how “warm spots” are also being identified in design using full-chip simulation. This is done, however, as a hedge for slight shifts of the process window on the production line-no one expects these software challenges to be a showstopper.
Our industry won’t make a clear process decision for the 22nm node for another couple of years, but the search for the best choice is underway, and at present there is no clear-cut favorite.
Super high-NA [1.75 NA] optical systems do not look promising. Large LuAG crystals have been grown, but transmittance remains an issue. No good Gen 3 organic fluids have been found, and the search has shifted to fluids doped with inorganic nanoparticles. Non-optical solutions may be required for 22nm.
The many champions of EUV point out that most “reasonable” projections for this technology show it will be less costly than double patterning, but EUV technology is not ready. The #1 problem remains the source power. Though both source suppliers reported good progress towards high power sources, both clearly feel the pressure of time-about 50× more power is needed, with about 18 months left before 22nm node decisions will be made.
The next big problem facing EUV development is a familiar but discouraging scenario: resist, which has been the pace-setting issue for 248nm and 193nm wavelength changes. Throughput models for EUV use optimistic sensitivity assumptions of 5-10 mJ/cm2. Linewidth error and line-edge roughness (LER) are serious problems-it looks like the resist roughness cannot be pushed below 3nm/edge. There were many good hallway discussions about likely causes, and a paper on molecular resist offered a promising solution, but in the end demonstrated no reduction of LER. SEMATECH has a major effort underway with member companies to collect and analyze the available data, in the hopes that the LER mechanism can be identified. Surface physics, not bulk properties, may be the cause.
Progress continues in the third pressing EUV issue, mask defects. The most numerous blank defects are now small pits in the blank surface. Work on the Synchrotron at UC/Berkeley is underway to look at EUV mask blanks with 13.5nm radiation to be sure there are no more undiscovered blank problems. Still, there is no large-area at-wavelength [13.5nm] defect scanner for controlling defects on EUV mask blanks.
Multi-beam direct write is enjoying a worldwide revival. The EC has launched a major program to push systems developed by Mapper and IMS to proof-of-concept tests and then bring one to production readiness. DARPA in the US has funded an effort at KLA-Tencor. Advantest has a multi-beam effort in Japan. Companies that make ASIC chips or small volumes of chips want a direct-write solution-design changes are so rapid for cell phone chips, for example, that these companies are pressing for a direct-write solution. The current throughput goal is 5 wafers/hr (300mm).
One of this workshop’s attractive features is its multidiscipline structure and randomized topics, allowing the world’s experts in each technology to attend and discuss their work. This year’s workshop included several papers from the magnetic disc industry, where processes are moving to small features faster than ICs-by 2011 they will need a 27nm full pitch process [13.5nm half-pitch]. Electron-beam direct write (EBDW) probably will be used to pattern dots on a master disc. It is only necessary to e-beam pattern every other dot, and the patterns can be crudely made. Then a block co-polymer is applied on top of the EBDW dots. The block co-polymer self assembles in a manner that fills in the missing dots, and smoothes the cylindrical walls, so a good master can be made. This will then be replicated, probably using nanoimprint lithography. While work remains, the progress in the last 18 months has looked very good. IC patterning might borrow the block co-polymer process to improve LER for very fine patterns-in fact, the disc-drive people may have discovered the way to extend optics to the 22nm node.
While inkjet printing is not often discussed as microlithography, it was reported at this workshop that color filters in LCD-TVs are now being produced using inkjet printing. This technique offers cost savings so great that it is expected to replace proximity printing in most production lines. The nanoimprint technique being considered by the magnetic disc people also uses a form of inkjet printing to apply the fluid just prior to imprinting. Maybe the flat-panel learning curve can be transferred to nanoimprint lithography.
This conference is about potential solutions to support the pursuit of Moore’s Law; just which solutions will win will be decided by each company. The cross-fertilization of ideas at this workshop should shorten the time to success. By the next Lithography Workshop in August 2009, we should know what processes work best for the 32nm node, and what processes are in the lead for the 22nm node. -Griff Resor, Resor Associates & SST Editorial Advisory Board.
Post-FET future discussed at IEDM
Silicon-based CMOS FETs will still be used in commercial ICs in twenty years, but it’s likely that completely new devices will also be in production. It seems highly likely that nMOS and pMOS FET “switches” will be used for mainstream logic and memory until 2015-2020, when such things as cross-bar architectures and quantum diodes may be needed. This is the group opinion of the world’s leading IC fab researchers, as discussed in a 2007 IEDM evening panel discussion moderated by Prof. Dimitri Antoniadis of MIT: “Looking Beyond Silicon-A Pipe Dream or the Inevitable Next Step?”
The industry will reach the practical limits of scaling planar bulk CMOS at different nodes for high-power logic, low-operating power logic, low stand-by power (LSTP) logic, and memory applications. “Transistor pitch scaling will be increasingly difficult due to stronger impact of parasitics and less effective stress engineering. Even if we can do it, power might limit what can be exploited,” opined Wilfried Haensch of IBM. Vertical scaling may be required to minimize parasitic capacitance, and high-mobility channel materials must provide the same or better density scaling potential as silicon devices to be attractive. Inherent variability in sub-22nm node devices will be daunting: pattern variation, random discrete dopants, the number of charges per unit device, and interface roughness (poly grain boundaries, high-k morphology, impurity scattering, etc.).
As an example of tough near-term scaling limits, for a physical gate length of 22nm (effective length 16nm), IBM saw that the extrinsic switching time depended upon the current flux through narrow raised source/drain (S/D) regions, with relatively faster switching in short and wide S/D. “There is no new switch in sight,” declared Haensch. “All candidates are either non-manufacturable or they cannot be wired up.” Lacking a replacement to the silicon FET, system performance will continue to increase with respect to historical trends due to architectural solutions-i.e., we’ll have systems with many ‘light-weight’ task-specific cores.
Akira Toriumi of the U. of Tokyo gave his educated opinion-based on first principles of manufacturing he learned at Toshiba-as to the best directions to go for a post-silicon future. He thinks that silicon microelectronics research will end in 2015, but any new materials, processing, and devices should be simple. “A one-dimension device like a wire, I don’t believe will be a solution; finFET will be a good candidate,” he said. He also advocates the use of germanium instead of compound semiconductors for new channels. “People are talking about Ge for pMOS and III-V for nMOS,” he noted, “but why don’t we challenge Ge CMOS? We can get metal S/D Ge nFETs.” For scaling we need to consider not just channel materials but also contact materials for these new channels.
We are now in a world using digital computing solutions that is “very safe and reassuring,” asserted Jean-Philippe Bourgoin of CEA-LETI. “If we look back at the work of von Neumann and Turing they had to understand the theory much more than we do now.” Audience member Paolo Gargini of Intel interjected that according to the theory of Heisenberg’s Uncertainty principle, Intel’s planned FET scaling will be limited in the year 2020. A member of Gargini’s research group mentioned the crossbar architecture under development in Stan Williams’ Lab at HP as a likely eventual replacement for the FET. (See Solid State Technology, April 2007, p.28.)
 Process flow for uniaxially strained {110} silicon nanowire transistor channels using an embedded SiGe source/drain for greatly improved pMOS. (Source: Samsung, IEDM 2007). |
The far limits of CMOS FET technology were shown by Samsung (Session 34, “CMOS Devices-Advanced Device Structures”) as experimental results of uniaxially strained {110} silicon nanowire transistor (SNWT) channels using an embedded SiGe Source/Drain for greatly improved pMOS performance (see figure). Starting with either SOI or bulk silicon wafers, they first grow embedded SiGe (20-40nm thick) and then Si. After hardmask patterning and a clever sequence of etching, the bottom of the grown Si {110} has become SNW floating above the removed SiGe, but the SiGe beneath the S/D remain, and the inherent SiGe/Si lattice-mismatch compressively stresses SNW to provide 1534µA/µm for pMOS. They saw nFET performance only ~15% lower regardless of {110} or {100} orientation, so good overall CMOS results are obtainable using {110}.
Beyond FETs and crossbar architectures lies a technology concept still mostly disbelieved by the mainstream: quantum electronics. The IEDM plenary session included a talk by Hiroyuki Sakaki, from the Toyota Technological Institute at the U. of Tokyo, on “Roles of Quantum Nanostructures on the Evolution and Future Advances of Electronic and Photonic Devices.” By controlling the electrons within nanoscale layered structures, quantum confinement results in effective two- dimensional electrons and the ability to form devices such as resonant tunneling diodes, quantum wire FETs, quantum dot lasers, and planar superlattice FETs.
However, commercial quantum electronics still remains out in the future. Use of carbon nanotubes (CNT) grown from catalyst particles shows promise, “but it has been very difficult to control the site selection, as well as other parameters,” according to Sakaki. Charge storage phenomena in quantum dots using either Si or InAs appear like the most likely near-term applications. Though if this is merely an extension of flash memory cell technology, does it really count as “quantum electronics?”
In 20 years, will we see a non-FET-based computer? The aggregate opinion seemed to be “yes,” but don’t expect people in the industry who have lived with it forever to be able to think “outside the FET” and develop something revolutionary. -E.K.
Novel device concepts explored at IEDM
There were many novel device concepts explored at the recent 2007 International Electron Devices Meeting (IEDM) in Washington DC. While several papers discussed high-k/metal gate dielectric concepts to cut leakage currents, there was also some discussion of performance enhancement by using metal for the source and drain. A novel source/drain implant technique enabling very low leakage silicon-on-insulator (SOI) CMOS for 65nm and below was reported by IBM. A new concept for optoelectronic tweezers that can trap and move objects down to the nanoscale was described by Ming Wu of the U. of California at Berkeley.
 Drain-sided tilted deep S/D implants in an SOI CMOS FET enable silicidization of part of the body near the source to tie the body to the source. (Source: IBM, IEDM) |
Performance enhancement using metal source/drain was explored in two IEDM papers. Metal could potentially offer less S/D contact resistance, but the problem is high-contact resistance at the source/channel interface due to a Schottky barrier. Larrieu, et al. from IEMN-UMR CNRS, STMicroelectronics, and UCL in France, showed how a low-temperature (<500°C) activation could be used for boron doping of PtSi source/drain in an implantation through silicide process that improved drive current by 50% compared to a dopant-free approach for thin-body SOI MOSFETs.
A Toshiba group showed how sputtering yttrium, ytterbium, and platinum onto an NiSi source and drain, and then annealing them to segregate the metals at the NiSi/Si interface, can achieve 0.1-1.5eV Schottky barrier reduction for both nMOS and pMOS. The process is reported to be thermally stable and scalable, offering improved contact resistance for future metal S/D CMOS.
A number of junction engineering techniques were investigated by IBM research groups to lower leakage current for partially depleted, low-power SOI CMOS devices down to 10µmA/µm with a 1.2V supply voltage. These included low damage junction preamorphization implants, a high-energy halo, and drain-side tilted source/drain implants. The key advance in the work is a novel method to tie the body to the source of SOI devices without modifying the device layout. Tilted S/D implants from the drain side move the deep source region away from the gate edge and expose the body under the source-side extension for salicide (see figure). This internal source-body tie was achieved in both nFET and pFET by using suitable tilt angle and extension conditions. Both the subthreshold slope and drain induced barrier loading (DIBL) were improved, although there was some increase in channel resistance resulting in a penalty of about 5% in IDSAT.
Optoelectronic tweezers that could trap and move colloidal particles with diameters down to tens of nanometers were developed at the U. of California at Berkeley. The technique combines the advantages of optical tweezers and dielectrophoresis, but uses 100,000× less power than optical tweezers, according to Ming Wu. Instead of handwired electrodes, the technique uses a projected light pattern on a photoconductive surface to create “virtual electrodes.” Since coherent light is not needed, low-cost sources such as a lamp or LEDs can be used instead of a laser. Light patterns are generated by a digital micromirror device are imaged onto the photoconductive surface, turning it into a programmable virtual electrode for DEP.
Wu reported that the technique has been used to trap single semiconductor nanowires, and also to manipulate cells in cell-culture media. -B.H.
Axcelis mixes it up at high energy with latest implanter
Completing its suite of Optima single wafer product implanters, Axcelis introduced the last offering in the family: the Optima XE high-energy ion implanter, which supports a broad energy range (10keV-4MeV) and targets the requirements of DRAM, NAND and NOR flash memory makers, as well as embedded memory and logic device manufacturers.
Generally speaking, the highest-energy implants are required for deep well formation in CCD applications, followed by NOR, NAND, DRAM, and then logic. The next highest energy is required for retrograde well formation in the same devices and in the same descending order. The company says its tool covers all these applications.
Based on the company’s RF Linac (RF linear accelerator) technology, the Optima XE operates in the single charge mode (vs. double or triple-charged ion modes). The advantage of running on single charge ions, according to Mike Chase, director of marketing for implant at Axcelis, is that the mode provides a higher beam current (i.e., more ions) than a double- or triple-charge mode. “Higher beam current means higher productivity,” he told SST, adding that “running implanters in the single charge state extends source life.”
Axcelis has productized two different versions of the RF Linac technology. The higher-energy version is used in the Optima XE, while the mid-energy range version is used in the Optima HE tool, which was also introduced at the same time.
According to Chase, the Optima XE’s ability to handle a broad range of applications appeals to fab managers seeking flexibility-particularly important in an industry increasingly working with high product mixes. To balance the load in a fab, end users will back up medium-current tools with high-energy ones, and divert some of that load if they can be productive in the medium-current application space, he explained. “A fab doesn’t run in steady-state-there are peaks and valleys in WIP moving through the fab,” he said. “If they can qualify the same recipes used on medium current implanters on high-energy implanters, it gives them the flexibility to divert WIP to high-energy tools when it makes sense.” -D.V.
MIT develops tiny, quick gas sensor
Engineers at MIT are developing a tiny sensor that could be used to detect minute quantities of hazardous gases-including toxic industrial chemicals and chemical warfare agents-much more quickly than current devices, says the MIT news office.
The researchers have taken the common techniques of gas chromatography and mass spectrometry and shrunk the sensors to fit in a device the size of a computer mouse. Eventually, the team, led by MIT Professor Akintunde Ibitayo Akinwande, plans to build a detector about the size of a matchbox.
Akinwande, a member of MIT’s Microsystems Technology Laboratories (MTL), and MIT research scientist Luis Velasquez-Garcia were planning to to present their work at the Micro Electro Mechanical Systems (MEMS) 2008 conference in January.
Scaling down gas detectors makes them much easier to use in a real-world environment, where they could be dispersed in a building or outdoor area. Making the devices small also reduces the amount of power they consume and enhances their sensitivity to trace amounts of gases, Akinwande said.
The device, which the researchers plan to have completed within two years, could be used to help protect water supplies or for medical diagnostics, as well as to detect hazardous gases in the air.