2007 International Technology Roadmap: MOSFET scaling challenges
02/01/2008
EXECUTIVE OVERVIEW
The 2007 International Technology Roadmap for Semiconductors (ITRS) makes projections covering the next 15 years, through 2022. For transistors, these projections include the scaling of key parameters such as gate length, gate dielectric thickness, transistor leakage and drain saturation current, transistor speed performance, etc. In addition, the ITRS assesses the main challenges to scaling MOSFETs, as well as the key technology innovations needed to overcome these challenges.
The ITRS transistor scaling is model-based, utilizing MASTAR, a detailed analytical MOSFET device model developed at ST Microelectronics. The projections are driven by meeting key targets for MOSFET performance and leakage. The key metric for MOSFET performance is the transistor intrinsic delay, τ = CV/I, where C is the MOSFET capacitance including parasitics; V = Vdd = the power supply voltage; and I = Id,sat = the drain saturation current. The shorter the delay, the better the MOSFET performance.
 Figure 1. Logic CMOS device categories. (Courtesy: K. Imai) |
Transistors for three different types of logic are specified in the ITRS: high-performance (HP), low standby power (LSTP), and low operating power (LOP). Figure 1 shows the types of applications, as well as the performance and leakage range for each transistor type. LSTP is generally used for mobile consumer applications, and is driven by meeting very low leakage current requirements to preserve battery life. As illustrated, it requires transistors with the lowest leakage current of the three types, and consequently the transistors have the lowest performance (i.e., highest CV/I). The resulting LSTP chip operation frequency is the lowest of all three types. In contrast, HP is used for high-performance stationary systems such as desktop PCs, servers, and routers, where system operating frequency is high and allowable leakage current is relatively high. Hence, it requires transistors with the highest performance (lowest CV/I), and as a consequence the transistors also have the highest leakage. LOP is used for mobile but higher-performance applications, such as notebook PCs, so these transistors are intermediate in performance and leakage. Since HP and LSTP transistors bracket LOP, this article will concentrate on HP and LSTP.
High-performance logic
The key target of ITRS scaling is to continue the historic 17%/year improvement in transistor performance, i.e., in CV/I. This is important because the transistor performance improvement is a critical component of the overall chip speed increase with scaling. The current mainstream transistor is planar bulk (or partially depleted silicon-on-insulator [PDSOI], which scales similarly to planar bulk).
Significant scaling difficulties have been encountered already, and are expected to worsen in the next few years as the gate length (Lg) is projected to scale to well below 30nm.
- With transistor scaling, Vdd is also scaled down. However, the threshold voltage, Vt, cannot be scaled down significantly, since the source/drain subthreshold leakage current, Isd,leak, increases sharply with decreased Vt, and it is important to keep Isd,leak within tolerable limits. Because Id,sat depends on (Vdd-Vt), the scaling of Vdd tends to reduce Id,sat and hence to make it difficult to improve the transistor CV/I performance at the desired 17%/year rate.
- Short-channel effects (SCEs, such as drain induced barrier lowering [DIBL]) are becoming very difficult to control as transistors are continuously scaled. This tends to lead to increased leakage current and to reduced Id,sat and hence reduced transistor speed (i.e., increased CV/I).
- Channel doping is becoming very large (both to set the threshold voltage [Vt] correctly and to control SCEs), leading to degradation in the mobility and to increased leakage current due to band-to-band tunneling.
- Scaling of the gate dielectric equivalent thickness, Tox, is limited by gate leakage current.
- With scaling, random dopant fluctuations and line edge roughness can cause significant statistical variation in Vt.
In order to help deal with these issues and to enable the targeted 17%/year transistor performance improvement while holding the leakage current to reasonable levels (around several hundred nAµm for HP logic), a number of key technological innovations are necessary. The first of these is enhanced mobility due to applied strain, which was implemented in production in 2004, and has been continuously improved since then. This mobility enhancement allows increased Id,sat, and is a critical enabler for the desired transistor performance improvement. To continue to meet the targeted performance improvement, it is essential that the enhanced mobility be maintained as transistors are scaled.
 Figure 2. Projected timeline for key transistor innovations. |
Figure 2 lists other key technological innovations that are needed to meet the transistor scaling goals. The ITRS projects 2008 implementation of high-k gate dielectric and metal gate electrode. The high-k reduces the gate leakage current and hence allows increased scaling of the gate dielectric thickness, while the metal gate reduces polysilicon depletion. As a result, the overall transistor scaling-and in particular the SCEs-can be significantly improved. Two new types of transistors, the ultra-thin body fully depleted SOI (UTB FDSOI) and the multiple-gate transistor (of which the finFET is the prime example), are projected for implementation in 2010 and 2011, respectively. Both of these transistor types typically have undoped, fully depleted channels. Because of their structure, the electrostatic integrity and hence the ability to control SCEs are generally superior to planar bulk transistors. Furthermore, the mobility should be superior because of the lack of doping. Finally, because Vt is set by the work function of the metal gate electrode, random dopant fluctuations do not impact the statistical variability of Vt for these transistor types. Because of all these advantages, the UTB FDSOI and the multiple-gate transistor will significantly improve scaling.
 Figure 3. High-performance logic: scaling of transistor speed metric, τ = CV/I. |
Figure 3 shows the scaling of CV/I for HP logic. The targeted 17%/year improvement is indicated by the dashed line. CV/I scales differently for the different transistor types. For planar bulk transistors, the scaling difficulties mentioned above result in an inability to meet the 17%/year target starting in 2009. Beyond 2009, the deviation from the dashed line increases, and after 2012 the SCEs become so significant that planar bulk scaling stops. For UTB FDSOI, for the reasons noted above, the scaling is improved and the 17%/year performance improvement is maintained for a longer time. However, beyond 2013, the CV/I curve deviates from the dashed line because, despite the advantages of this structure, eventually SCEs increase significantly. Beyond 2015, the SCEs become so prominent that scaling of UTB FDSOI MOSFETs stops.
For multiple-gate transistors, the 17%/year performance improvement is maintained through 2019. Beyond that, the CV/I curve deviates from the targeted improvement, because SCEs increase notably. Clearly, the multiple-gate transistor scales the best, while the UTB FDSOI scales in between the planar bulk and the multiple-gate. The superiority of the latter transistor type is due to the multiple gates, which improve the electrostatic integrity and hence the control of SCEs with scaling. We project that the ultimate MOSFET (for sub-15nm gate length transistors late in the Roadmap) is the multiple-gate transistor. Note that multiple parallel paths are envisioned, where for several years two or even all three transistor types coexist. For HP logic, all three types coexist during 2011 and 2012, while planar bulk and UTB FDSOI coexist during 2010, and UTB FDSOI and multiple-gate transistors coexist from 2013-2015. This is believed to be a realistic picture for the industry: Some companies will persist in using planar bulk longer than others, while others will switch to UTB FDSOI or multiple-gate transistors earlier. Each company is uniquely driven in its device choices by its technical strengths, its products and market strategy, and its strategic plan.
Referring again to Fig. 2, the final innovation is the use of advanced, enhanced transport solutions sometime after 2015. These advanced solutions could include III-V and/or germanium channels, or perhaps more exotic solutions, such as the use of nanowires or carbon nanotubes. This type of advanced solution may be required to boost the transistor performance to the required levels, since it appears unlikely that silicon channel (or SiGe channel) MOSFETs will meet the 17%/year performance improvement target late in the Roadmap, even with multiple-gate structures and strain-enhanced mobility. The dotted section from 2015-2017 indicates that there is considerable uncertainty as to when such advanced solutions will really be needed.
LSTP logic
For LSTP logic, where the most important concern is low leakage to preserve battery life, the ITRS scaling target is to maintain a low level of source/drain subthreshold leakage current, Isd,leak. This level is set to 30pA/µm over the life of the Roadmap, consistent with industry practice. The transistor performance is improved as rapidly as possible while meeting the leakage target. To meet the targeted low leakage requirements, the key technology innovations are by and large the same as for HP logic, with somewhat different timing (Fig. 2). High-k gate dielectric and metal gate electrode are projected for 2008, the same as for HP, but UTB FDSOI and multiple-gate transistors are both delayed until 2012. The need for the advanced, enhanced transport solutions is clearly delayed well beyond 2015 and probably beyond 2017. As with HP logic, multiple parallel paths are projected for LSTP logic.
 Figure 4. LSTP logic: scaling of τ = CV/I. |
Figure 4 plots the scaling of CV/I for LSTP. The curves for LSTP are generally similar to the HP curves, although the rate of improvement is 14%/year, rather than 17%. To meet the very low Isd,leak target for LSTP, Vt needs to be relatively high, resulting in reduced Id,sat. Hence, CV/I is increased, and in particular, it is larger for LSTP than for HP (for example, in 2007, CV/I for HP is ~0.6 ps, while it is ~2 ps for LSTP). The same scaling difficulties are encountered as for HP logic, and as a result, the CV/I curves deviate from the 14%/year improvement rate. As with HP, multiple-gate transistors scale the best, and are the ultimate MOSFET late in the Roadmap, while planar bulk transistors scale the worst, and UTB FDSOI transistors scale in between.
Conclusion
The three types of logic have different key technology targets, which distinctly drive the transistor requirements for each. High-performance (HP) logic is focused on transistor performance, and the historic 17%/year improvement in the transistor CV/I performance metric is targeted and satisfied in the ITRS projections. However, the leakage current is relatively large, in the range of several hundred nA/µm. To meet the performance and leakage targets, key technology innovations are required, including high-k gate dielectrics and metal gate electrodes in 2008, ultra-thin body fully-depleted SOI MOSFETs in 2010, and multiple-gate MOSFETs in 2011. The ultimate scaled MOSFET is expected to be multiple-gate, possibly with advanced, enhanced transport innovations such as III-V channels and nanowire MOSFETs. Low standby power (LSTP) logic is focused on very low leakage current, and the transistor leakage is held to 30pA/µm over the course of the Roadmap. However, the CV/I performance metric is 23× times slower than for HP logic. The same key technology innovations are required as for HP logic, although the timing is somewhat different. Finally, low operating power (LOP) logic is intermediate in transistor performance and leakage between HP and LSTP logic.
Acknowledgments
The author gratefully acknowledges the contributions of his many colleagues on the Process Integration, Devices, and Structures (PIDS) Working Group of the 2007 ITRS. The author says it was a pleasure to work with so many top technical experts from around the world, and the transistor scaling projections that are discussed in this article are the product of intensive collaboration with them.
A special acknowledgement is due to Frederick Boeuf and Thomas Skotnicki of ST Microelectronics for their help with the MASTAR device modeling software, which was heavily utilized in generating the MOSFET scaling projections in the PIDS chapter. They made the MASTAR program available to the ITRS and helped significantly in applying it effectively to the PIDS work.
References
For a list of references to this article, please check out the February issue on the SST web site at www.solid-state.com.
Peter Zeitzoff received his BSE and PhD in electrical engineering from Princeton U. He has worked in the IC technology field for over 30 years. In 2006, he joined the CMOS Research Department of Freescale. Since 2001, he has chaired the US Region’s Process Integration, Devices and Structures Technology Working Group of the International Technology Roadmap for Semiconductors. Contact him at: [email protected].