Technology News
01/01/2008
Toshiba, SanDisk ramping 43nm NAND flash with HK+MG, 3b/cell
Toshiba Corp. and SanDisk Corp. aim to increase their share of the NAND flash market by bringing down costs, as they accelerate the ramp of their new Yokkaichi Fab 4 next year, introducing 43nm geometries, high-k/metal gates, second generation 1.3NA immersion lithography, and 3 bits per cell.
Executives from both companies detailed their current production plans and future roadmap for flash memory technology to Solid State Technology partner Nikkei Microdevices in Tokyo.
Toshiba aggressively projects demand for NAND flash storage capacity to more than double every year through 2010, for a 30× total increase over 2006 (see Fig. 1), dependent in part on falling price/bit. So the companies now plan to ramp Fab 4 to 80,000 wafers/month in 2008 and 210,000 in 2009, a 40% increase over the original plan. “We initially planned Fab 4 for 150,000 wafers/month, for which we and Toshiba planned to invest a combined $5.5 billion (¥600B),” SanDisk chairman and CEO Eli Harari told Nikkei Microdevices. “Now that planned capacity has been increased to 210,000, investment will be higher.”
 Toshiba sees 30× jump in flash memory demand by 2010. (Source: Toshiba, Nikkei Microdevices) |
Toshiba will put some 70% of its $6.5B/¥715B capital investment budget for 2008-2009 into NAND flash, primarily toward the additional capacity at Fab 4. With that fab now slated to reach full capacity by 2009, the company says it will decide on adding an additional flash fab by this spring. Toshiba officials say they could fill only 75% of orders this fall. Harari says SanDisk’s wide range of customers makes its demand more stable than at some competitors.
Volume production was to start in December at 56nm at Fab 4, with first phase installed capacity of 42,000 wafers/month. In early 2008, production will start to switch over to 43nm, which will be the fab’s primary output. The partners introduced immersion lithography for 56nm in Fab 3 in early 2007, and ramped that to 90% capacity within the year.
“We struggled over the ramp of immersion,” Yokkaichi fab GM Noriyoshi Tozawa told Nikkei Microdevices. “But now that it’s in use in standard production, the switchover to 43nm should go smoothly.” He notes that for 43nm the fab has added new 1.3NA immersion scanners and new deposition tools for high-k/metal gates. A hafnium oxide is used for the inter-poly dielectric separating the control gate and the floating gate, and a metal silicide replaces polysilicon in the control gate. The improved materials allow the floating gate to be made flatter, reducing the cross talk between cells for more reliable data writing and reading.
The companies count on adding another level of multilevel cell technology to significantly bring down costs by increasing the data storage capacity of each chip. Toshiba reports that almost 100% of its 56nm production is now 2 bits/cell, and development of technology for 3 bits/cell is almost completed. It plans to start shipping samples before the end of 1Q08, and expects to start commercial production in the second half of next year.
Storing 3 bits/cell requires distinguishing eight different voltage levels, but adds 50% more storage capacity per chip for essentially the same cost. It could also mean Fab 4 output in bit count in 2008 could be up 5×-8× from 2007. Toshiba/SanDisk is apparently the only memory supplier to date to announce a target shipping date for 3 bits/cell NAND flash memory. Harari notes that they expect to commercialize an improved multilevel cell product in 2008 that meets solid state computer drive requirements. He says his company has started supplying solid state drives to IBM Corp. and Dell Inc., and Intel Corp has decided to use them for low cost personal computers.
Toshiba plans to keep using its floating gate structure through the 30nm generation, now targeted for sample shipments in the second half of 2009 and volume production in early 2010. But the company will need to develop another new set of materials, probably a fully silicided metal electrode for the control gate, as well as a better high-k inter-poly dielectric. And Toshiba expects to use double patterning immersion as the only practical way to get 30nm features at that date.
Toshiba Semiconductor President Shozo Saito says 2009-2010 is also its target for introducing 4 bits/cell storage technology. The company has demonstrated a 16Gbit chip using 4 bits/cell with a 70nm design rule; the 168mm2 chip is only about 15% bigger than a 2 bit/cell version. With 16 different closely-spaced voltage levels to distinguish, though, writing speed remains slow (<1Mbyte/sec). SanDisk’s chairman Harari notes the prototype using controller technology from its Israeli acquisition, msystems Ltd., underperformed the 2 bit/cell product, so considerable development work remains.
 Toshiba roadmap: High-k/metal gates enable flatter floating gate structure, reducing cross talk between cells. (Source: Toshiba, Nikkei Microdevices) |
At the 20nm generation, even Toshiba will have to give up its floating gate for a new cell structure. Hiroshi Nakai, head of flash memory strategy, says the company will likely turn to a SiN charge trap cell, aiming for production in 2011-2012-likely with 13.6nm EUV lithography, which Nakai says now seems likely to be available by 2011. At 10nm, another new and probably 3D structure will likely be required, based on charge trap or cross-point junctions.
“I think it will be difficult to make floating-gate cells beyond 22nm, so we’re developing 3D structures, using the one-time-programmable 3D memory know-how we acquired with our purchase of Matrix Semiconductor,” says SanDisk chairman Harari. “We’re concentrating on cross point cells like Matrix’s that don’t use transistors…though for NAND flash, we need to develop a material that can be re-written, not just programmed once like Matrix’s.”
—Paula Doe, Contributing Editor
Spansion makes diversity play with SONOS-based MirrorBit technology
Pure-play flash memory provider Spansion has announced plans for its next-generation MirrorBit ORNAND architecture based on its proprietary charge-trapping storage technology. The “MirrorBit ORNAND2” family, utilizing 45nm processes, will use a SONOS-like memory cell connected in a NAND memory array.
According to Bertrand Cambou, president and CEO of Spansion, the current manufacturing strategy includes three sources for the MirrorBit ORNAND family of products at 65nm: the Spansion 1 fab in Japan, which opened in September and is expected to generate revenue in 4Q07; and production at TSMC and at SMIC, both of which will follow sometime in 2008, with TSMC going first. Manufacturing at 45nm will start in 2008 at SP1, followed by as-yet-unannounced foundry production. Today, MirrorBit manufacturing is done with 90nm processes at Spansion’s Fab 25 in Austin (200mm) and at TSMC (300mm).
Not only does Cambou believe the com‑ pany has a “massive” cost advantage with its triple-sourced strategy, he told SST that competitors in the NOR space are generally using trailing-edge floating gate technology and are lagging behind with the use of charge-trapping technology. “We have 10 years of experience with charge-trapping,” he said. “We started to work on it in 1998 and we have a strong IP portfolio.” Some industry experts believe that traditional floating gate NAND flash technology will encounter a serious charge storage problem at advanced nodes, starting at around 40nm, hence the anticipated move to charge-trapping.
Cambou noted that the company’s recent agreement to acquire Saifun Semiconductors will further strengthen its portfolio. Under terms of the agreement, Saifun will be operated as a wholly owned subsidiary and drive Spansion’s technology licensing business. “We think that right now, the key leading NAND flash companies will be moving to technology that is similar to MirrorBit,” Cambou said, “so we have an opportunity to help that transition by licensing our technology—enabling Spansion to diversify into NAND and the licensing business.”
Cambou characterized the ORNAND design as a NOR core with a NAND footprint. In the NAND-type of design, the cell voltage is less and fewer transistors are needed in the periphery, he told SST. Because the SONOS ORNAND architecture uses 25% fewer manufacturing steps than the NOR technology (at the same technology node), the manufacturing flow can be simplified by eliminating steps. Additionally, because of the smaller cell size (for NAND, i.e., greater density), Cambou said that ORNAND costs are 50% of those of NOR, when compared in the same factory.
Approximately $300M of Spansion’s revenue in 2007 is expected to come from ORNAND1, a product line targeted at the high-end cell phone market, and about 80% of the company’s revenue comes from MirrorBit technology, according to Cambou. Another architecture based on MirrorBit technology, Eclipse (announced in April 2007), combines MirrorBit NOR, ORNAND and Quad Flash memory on a single die, also for use in cell phones. –D.V.
KLA-Tencor ellipsometer now goes to 150nm; ONO stacks resolved
With greater complexity in ever thinner films used in manufacturing advanced CMOS transistors, such as the gate dielectric stacks formed by atomic layer deposition and graded diffusion, there is vital need for additional metrology capability in the fab. Spectroscopic ellipsometers (SE) have been used for decades to provide thickness and composition information for thin dielectric films, and expanding the wavelength of the spectrum inherently provides more information.
Most broadband SEs have been limited by optics hardware to resolving as low as 190nm wavelengths, but a lot of interesting information regarding dielectrics can be found down below 190nm. In particular, for complex siliconOxide-siliconNitride-siliconOxide (ONO) dielectric stacks (see figure), insight down to 150nm allows for thickness and composition information to be extracted from a single measurement. With this in mind, KLA-Tencor modified its broadband SE tool to push the wavelength from a 190nm lower-wavelength limit down to 150nm.
 Thin ONO stack process control enables greater sensitivity in 150-190nm range to thickness changes. (Source: KLA-Tencor) |
The 8500 is the first tool in a newly named Aleris product family for KLA-Tencor, and in coming months “there will be other tools in the family to address other modules in the customer fab,” said Namrata Vora, product marketing manager in the company’s Films and Scatterometry Division. The company claims >25 tools in the Aleris family are already in the field, with the 8500 reportedly in production for gate-length control at 65nm, and for multilayer interconnect measurement.
The tool uses patented reflective optics for focusing, ensuring the same focal points for different wavelengths, explained Vora. “This lets us use a much smaller spot size, allowing us to measure product wafers.” Compared to the prior generation tool, the tightened optics allow for the minimum spot or box size to be reduced by ~20%. Low spectral distortions minimize noise levels, which helps with tool matching for manufacturing.
“To prevent absorption of the wavelength at 150nm, we have to purge the optics with an inert gas but no vacuum is needed,” reminded Vora. This latter comment perhaps refers to startup OEM Metrosol’s vacuum ultraviolet (VUV) SE tool (released in July), which requires vacuum pumps and chambers but does allow for further insight down to 120nm.
The 8500 is more than just an extended range SE, however, since it has many additional handling and inspecting capabilities tuned to the unique requirements of manufacturing ICs at advanced device nodes. For example, laser desorption removes airborne molecular contamination from up to eight hours of queue-time exposure, to ensure accurate measurements.
Stress measurement on the 8500 is done using laser rastering across the wafer and sub-millimeter spatial resolution at the detector to measure as little as 10µm of bow due to thin films. The measurement technique is much faster than the former z-axis focus. –E.K.
Tech Briefs from Japan
Sharp improves ozone water wafer cleaner
Sharp Manufacturing Systems has created a wafer cleaning system that uses hot, concentrated ozone water with sustained high concentrations to more effectively dissolve and remove photoresist and other organic contaminants, according to the Nikkei Business Daily.
Typical ozone-water removal methods used as a gentler cleaner than sulfuric acid (which also costs chipmakers more than ¥10B/~$90M annually) oxidize and dissolve unwanted on-wafer compounds, with ozone concentration of 75ppm in 80°C water (the higher the temperature, the lower the concentration). But the company has figured out how to vary the pressure to prevent the ozone concentration from declining during heating, which improves the ozone concentration by nearly 50% to 110ppm at 80°C.
The technology is being combined with other equipment into a cleaning system, to sell for around ¥50M (US ~$460K), the paper noted. Sharp Manufacturing hopes to sell 10 units next year, and 70 by 2010.
TDK tips way to purge FOUP gases
TDK has developed a way to quickly expunge air inside 300mm wafer front-opening unified pods (FOUPs) when entering or leaving cleanrooms, which otherwise can oxidize and damage wafers and lower yields, notes the Nikkei Business Daily.
The new technology jets inert nitrogen gas from the side of the FOUP for ~2min to drive out oxygen and residual gases from inside the case, lowering the oxygen content to ~13%. The gas is then blown from a nozzle above the FOUP and carried to the sides for another 2min to further reduce oxygen concentration to 2%, and the FOUP case is sealed.
The new FOUP-cleaning technology will be incorporated into TDK’s wafer load ports starting in April, aiming for 100 unit shipments in the first year, and increase to 1000 units/month over the next three years, the paper noted.
New additive limits tin whiskers
C. Uyemura & Co. says it has developed an additive that prevents formation of “tin whiskers” on circuit boards and other electronic components.
Circuit boards historically have been plated with tin-lead plated finish to prevent oxidation and improve soldering, but the switch to lead-free tin plating has exacerbated the problem of “tin whiskers,” needle-like metal crystals that can grow spontaneously on finished surfaces, potentially causing current leakage and shorting. Using other plating materials avoids the problem, but these materials can be up to twice as expensive, explains the Nikkei Business Daily.
The company’s new “GRX-70” additive, a mix of surfactants and organic compounds, doesn’t entirely eliminate tin whiskers, but it does help regulate their length to just 3-5μm (half the usual size) to better distribute expansion at the interface between the tin plating and copper wiring, the force behind whisker growth, the paper notes. Samples of the additive are now being sold at roughly ¥2000/liter (~US $18/l).