Issue



IEDM shows real details of materials technology, devices


01/01/2008







EXECUTIVE OVERVIEW

Over 1600 technologists gathered in Washington, DC, last month to explore a wide range of innovative ideas at the 2007 International Electron Devices Meeting (IEDM). Boosting performance as the shrink heads below 45nm was the goal of many new CMOS-based schemes. There were 237 papers from all over the globe, about a third of the 695 submitted. The news centered on high-k metal-gate transistors and using elements from all over the periodic table, as these two articles describe.

HKMG’s real details shown

The first big news to come out of last month’s IEDM concerned high-k/metal-gate (HK+MG) transistors for 45nm node and beyond processing. With many parallel sessions covering the most important technology trends in IC manufacturing, it is impossible to mention all of the great results presented by teams from around the world (apologies to: ST/NXP/Freescale, Fujitsu, MIRAI, NEC, SELETE, Sony, Toshiba, and TSMC).

Presenting on behalf of 53 co-authors, Intel VP Kaizad Mistry disclosed some real details of the company’s latest 45nm process technology featuring HK+MG. Finally answering the gate-first or gate last question with “both,” Intel has decided that the tough integration challenges for high performance logic can be best met with HK first but MG last processing. The transistors feature 1.0nm equivalent oxide thickness (EOT) dielectric, based on an atomic layer deposition (ALD) of a hafnium-based compound. In an evening event sponsored by Chipworks, Dick James revealed some additional details found in an Intel 45nm Xeon E5410 microprocessor torn apart last month: ~42nm minimum metal gate length; ~25nm silicide/gate spacing; ~1.1nm SiO2 + 1.2-2.0nm Hf-based dielectric. “That has to be more than 1nm EOT, but I suppose it depends on how you do the rounding,” quipped James. A close-up TEM shows that the Hf-based dielectric appears to be amorphous. The metal gate stack reportedly involves tantalum, titanium nitride, titanium aluminum, and aluminum. “We’ve come full circle-back to aluminum gates,” said James.

pMOS performance is improved by increasing the Ge content of the embedded SiGe to 30% (from 23% @ 65nm, and 17% @ 90nm) and by reducing SiGe proximity to the channel. Lithography utilizes 193nm dry patterning, though some masks require two exposures in two resist layers along with a sacrificial hardmask. Transistors feature 35nm physical gate length, ultra-shallow junctions, and nickel silicide. Drive currents are benchmarked at 1.0V, a low 100nA/µm IOFF and at 160nm contacted gate pitch. The pMOS drive current is 1.07mA/µm (51% improvement over 65nm), while nMOS drive current is 1.36mA/µm (12% better than 65nm). SRAM arrays with cell sizes of 0.346µm2 and 0.383µm2 (performance dependent) and multiple microprocessors are already in volume production, with claimed excellent yields. The figure shows Intel’s 45nm high-k and metal gate pMOS transistor.


TEM micrograph of 45nm Intel high-k and metal gate pMOS transistor. (Source: IEDM2007 10.2)
Click here to enlarge image

Intel’s gate-first/last HK+MG process flow for 45nm transistors is as follows:

  • STI, well, and VT implants,
  • ALD (18-20Å) of HK gate dielectric,
  • polysilicon deposition and gate patterning,
  • source/drain extensions, spacer, Si recess and SiGe deposition,
  • source/drain anneal, Ni salicidation, ILD0 deposition,
  • poly opening CMP, poly removal,
  • pMOS work-function metal deposition,
  • metal gate patterning, nMOS workfunction metal deposition, and
  • metal gate Al fill and Al CMP, etch-stop layer deposition.

IMEC and its partners (TSMC, Matsushita, Infineon, Samsung, and NXP) showed a low VT CMOS gate-first HK+MG using TaC-based metals and laser-only annealing. Symmetric low VT values of ±0.25V and unstrained IDSAT of 1035/500µA/µm (for nMOS/pMOS respectively) at IOFF = 100nA/µm and VDD = 1.1V were demonstrated on a single wafer. To do so required Hf-based high-k dielectric capping layers of lanthanum oxide (La2O3) for nMOS and aluminum oxide (Al2O3) for pMOS to lower EOT from ~1.7 to ~1.5nm while maintaining the same target VT. HK-caps in combination with a laser-only activation anneal maintain band-edge equivalent work-function (EWF) and minimal EOT re-growth. La2O3 thickness control allows for VT tuning from 0.2-0.6 for nMOS. HfSiO shows lower VT and higher mobilities compared to HfSiON. The laser-only anneal further results in improved LG scaling of 15nm and a 0.2nm TINV reduction over the spike reference. Lam etchers were used for gate patterning. IMEC has also been working on HK+MG for finFETs.

Prof. A. Toriumi, et al. (U. of Tokyo, MIRAI-AIST, MIRAI-ASET) presented on “Materials science-based device performance engineering for metal gate high-k CMOS.” EOT is based on k, which is based on the internal field and the polarizability of the material itself. HfO2 has monoclinic phase, but adding lanthanum, silicon, yttrium, and/or titanium can change the phase to cubic or tetragonal, while the k increases to ~30. Adding La2O3 increases the crystallization temperature up to 800-1000°C (over the range of 20-40% incorporation), and the amorphous phase has the best overall properties. Regardless of composition, leakage current depends only on the physical thickness, which shows that the leakage mechanism is pure direct tunneling. Thus, using higher k films with equal EOT (down to ~0.5nm) significantly reduces the leakage. Flat-band voltage shift has been clearly shown to be determined only by the dipoles formed at the bottom interface between SiO2 and HK, and not by the HK to MG interface. Scattering effects should be correlated to both the material itself and oxygen vacancies in the material.

Important information is being learned about nMOS/pMOS boundaries, according to H. Rusty Harris from SEMATECH, who gave an amazing presentation on a flexible, simplified CMOS using HK+MG on Si{110}. “What we have shown is that if we add capping layers on top of the dielectric, we do not see mobility degradation,” he said. Carrier mobilities depend upon crystallographic orientation, and changing from standard {100} to {110} orientation allows for mobility increase of 3× for holes, while electron mobility drops by ~1/2. Mixed orientation-Si{100} for nMOS and Si{110} for pMOS-has been examined but process complexity, cost, and variability seem unattractive. Data for Si{110} planar CMOS is relatively similar to a multiple orientation approach (with much lower manufacturing cost), though a pre-amorphosizing implant is used to minimize diffusion which is faster in {110} compared to {100} silicon. Even better results should be seen with finFETs, which inherently require orientation engineering. Using large 0.25µm planar transistor lengths (not short enough to fully realize the nMOS improvements), they showed that ring oscillators were nearly equivalent regardless of {110} or {100}. Sub-threshold leakage is an important factor in LSTP optimization, and gate-induced drain lowering (GIDL) is the second biggest factor in off-state power. Without even optimizing the process flow for {110}, using {110} lowered GIDL by an order of magnitude compared to {100}.

CEA-LETI-MINATEC/Soitec use TiN metal over HfO2 HK gate dielectric to explore the limits of HK+MG with SOI substrates. From a historical perspective, Takagi, et al. (IEDM 1997) showed that long-channel transport conditions effectively degrade electron mobility as dielectric thickness decreases. Gate lengths from 18nm to 10µm were fabricated, all with widths of 10µm, EOT 1.7nm, and 145nm BOX thickness. They consider ballistic carriers may primarily determine the conduction in sSOI short-channel devices, and invoke a “ballisticity rate” to partly explain the influence of surface roughness scattering. Si thickness down to 2.5nm for SOI has been used for both HP (ION = 780µA/µm) and LP (IOFF = 10pA/µm) devices.

Meanwhile, IBM and its partners missed out on getting a HK+MG paper into IEDM this year, and instead issued a press release about 32nm development. Having publicly committed to gate-first processing, Freescale researchers in the alliance have published a paper in the Journal of Applied Physics on the crystalline phases formed using zirconium along with hafnium-oxide. Hafnium zirconate (HfZrO4) alloy gate dielectric and hafnium dioxide (HfO2) films were formed by atomic layer deposition using metal halides and heavy water as precursors. -E.K.

Darts hit elements all over the periodic table

While current mainstream CMOS approaches, using strain engineering and metal/high-k dielectric gates, were covered extensively at IEDM, there were also a wide range of further-out alternatives, suggesting that darts had been tossed at periodic table charts all over the world.

Germanium and silicon germanium (SiGe) were predominant, but there were many other devices incorporating III-V compounds, metal source and drain, and even hints of future circuitry based on carbon rather than Si or Ge. Carbon-based nanoelectronic technology using graphene even won a catchy new name: “pionics.”

A very promising demonstration of how compound semiconductor devices might be integrated onto a silicon substrate was presented by a group from Intel and IQE (Bethlehem, PA). An enhancement-mode quantum well (QW) transistor using indium-gallium-arsenide InGaAs was heterogeneously integrated onto silicon using a composite buffer only 1.3µm thick. The QFET is very promising for high-speed, low-power logic due to high electron mobility and low leakage. This seamless integration of a high-performance QFET suggests that logic blocks of such devices could be coupled with mainstream SiCMOS platforms for future microprocessors, the authors concluded. The quantum well device with an 80nm gate length had a +0.11V threshold voltage with an ION/IOFF ratio of 2150 with a 0.5V gate voltage swing. Subthreshold slope and drain induced barrier lowering (DIBL) were better for enhancement-mode than depletion-mode devices, they reported.

A sub-50nm compound semiconductor high-electron-mobility transistor (HEMT) also set a new speed record, achieving an extrapolated Fmax of over 1THz, as reported by a group from Northrop Grumman Space Technology and the Jet Propulsion Labs (JPL). The extrapolation was based on the successful demo of a three-stage low-noise millimeter IC amplifier working at 340GHz with over 15dB gain. The authors believe they can achieve 600-700GHz amplifiers with next-generation designs, pushing the limits for military and telecom systems as well as radio astronomy. The InGaAs/InAlAs/InP HEMT incorporates a T-shaped gate as small as 35nm formed using e-beam lithography.

Another record, an ultrahigh blocking voltage of 8300V which could be useful for high-power systems such as hybrid vehicles, was achieved for an AlGaN/GaN heterogeneous transistor (HFET) on sapphire with thick poly-AIN passivation by a group from Matsushita/Panasonic. Via holes were drilled through the etch-resistant sapphire by a high-powered laser. The device achieves a specific on-state resistance of 186Ω.cm2 with an Imax of 150mA/mm.

A room-temperature electrically pumped Ge semiconductor laser, potentially useful for light generation for an IC, was developed by a group from National Taiwan U. They used a simple metal-insulator semiconductor (MIS) structure, with a thin (~2nm) tunneling insulator to allow carrier tunneling between an electrode and the semiconductor. A pair of cleaved {111} planes perpendicular to the plane of the junction forms a Fabry-Perot cavity. The device is 48µm wide with a 1-2mm cavity length. The authors suggest that the Ge laser could be integrated onto silicon by epi or wafer bonding, and an even better laser may be feasible by taking advantage of the SiGe junction.

Pionics, or graphene nanoelectronics, was the topic of an overflowing session. Walt deHeer of the Georgia Institute of Technology said he was surprised his paper was accepted due to the early phase of this work on deposited hexagonal carbon like that of carbon nanotubes (CNT). The major difference is that CNTs grow in an uncontrolled tangle while the deposited graphene forms thin films on a SiC wafer. In-plane sigma bonds in the carbon form the strongest bonds known but groups of atoms form p-electron orbitals in what is called pi bands, hence the name “pionics.” The pi band mass is zero, so carrier velocities are independent of energy. In addition to charge and spin, they are characterized by chirality. Successive layers in the hexagonal motif are rotated about 2.5°, so there is little interlayer coupling.

Similar to CNTs, metallic or semiconducting graphene ribbons can be created with the bandgap inversely proportionally to the ribbon width due to quantum confinement. The graphene layers can be patterned using microelectronics techniques to form both transistors and interconnects. Graphene mobilities of 104cm2/Vs have been demonstrated, promising higher speeds and lower power than is possible with silicon, deHeer said.

Obtaining bandgaps suitable for room-temperature operation would require nanopatterning beyond present capabilities, however, so a chemical modification method for bandgap control would more expedient at present, he explained. The excitement about pionics at IEDM is shared by DARPA, according to a source at the session, and a major development program is planned for this emerging technology.

Another graphene paper from the U. of Florida in the US and U. of Pisa in Italy did a performance comparison of two types of graphene nanoribbon devices: Schottky barrier and MOSFETs. The MOSFET has superior parameters and would be less impacted by potential defects, so this type of device would be preferable.

The JJ Ebers award fittingly went to Stephen J. Pearton, a Tasmanian with a dry wit, who was a pioneer in developing processes for compound semiconductors when at Bell Labs. Pearton noted in his acceptance that compound semiconductors and silicon technology now appear to be merging to some extent, and he congratulated the silicon community for “catching up.” -B.H.