Embedded DRAM makes inroads into SoC devices
01/01/2008
EXECUTIVE OVERVIEW
This month, presents a special preview of the January edition of Chip Forensics, an online column by Dick James, senior technology adviser at Chipworks, a specialty reverse engineering company that takes apart ICs and electronics systems in order to provide engineering information for its customers. In this column, James examines the graphics chips in game systems that have started using embedded DRAM, specifically, the Sony PlayStation 2 (PS2) and the Microsoft X-box 360. He chose these two chips, both 90nm technology devices, because they reflect the process split in commodity DRAM, with some products using capacitors formed by trenches in the substrate (“trench” DRAM) and others building the capacitors above the substrate surface (“stack” DRAM).
For a number of years now, we have seen increased integration of multiple functions onto silicon, creating the class of products known as system-on-chip (SoC). Memory in the form of SRAM has been widely integrated for decades into microprocessors and FPGAs; even though DRAM has had some media hype extolling its advantages, we have seen limited use of it on the same silicon as other functions. It has been around, but usually in niche products where space and performance constraints justify the extra processing cost.
However, now we have consumer products as the major new driver for the industry, particularly in the graphics-processing field. This requires the movement of massive amounts of data as quickly as possible into and out of the processor. For seriously large amounts of memory, it is still necessary to use commodity DRAM co-packaged with a processor chip-for example, the iPhone applications processor has a 1Gbit DRAM die attached in a package-on-package configuration.
In cases where a more modest memory density will do, the graphics chips in game systems have started using embedded DRAM, and I thought it would be interesting to look at examples out of the Sony PlayStation 2 (PS2) and the Microsoft X-box 360. They are both 90nm technology devices; the X-box chip is made by NEC, and the PS2 processor is fabbed by the Sony/Toshiba consortium in their joint fab in Oita. These two reflect the process split in commodity DRAM, with some products using capacitors formed by trenches in the substrate (“trench” DRAM), and other building the capacitors above the substrate surface (“stack” DRAM).
 Figure 1. PS2 processor chip de-layered to M1. |
The PS2 “EmotionEngine + GraphicsSynthesizer” chip was one of the first 90nm parts to hit the market, so it was fairly remarkable that it had 72 Mb of embedded DRAM included. It was fabricated using Sony’s ASC9 process [1] using five levels of copper and an aluminum bond pad layer. Figure 1 is the die de-layered to the 1st metal level (M1), showing the memory blocks in the device, with the DRAM at one end of the die.
 Figure 2. SEM cross-section of DRAM cells in PS2 processor chip. |
Back when both Toshiba and IBM were in the commodity DRAM business, they had a development alliance in which Toshiba adopted the IBM style of trench-capacitor DRAM. Both have since exited that market, but they still use the technology for embedded dynamic memory. Consequently, the PS2 chip uses trench capacitors in the substrate, as shown in the cross-section in Fig. 2.
 Figure 3. DRAM block stained to show n-well. |
We can see the trenches going deep (9.5µm) into the P-substrate, surrounded by the n-doped cell plate, and with a p-well at the top for the NMOS access transistors (wordlines). The cell plate was doped by a long out-diffusion from the trenches, so that the individual diffusions merged together to give a continuous buried n-well, which serves as the common plate of the DRAM capacitor (Fig. 3). The well was relatively highly doped at >1019 carriers/cm3 to increase the cell capacitance, claimed at about 40fF. This diffusion was masked from the upper part of the substrate by a ~35nm thick collar oxide, seen in Figs. 4a and 4b.
 Figure 4. Details of Sony e-DRAM capacitor structure. |
The trenches were filled with n-doped polysilicon, and connected to the source/drain diffusions through a gap at the top of the collar; the lower part of the trench was lined with a NO (nitride and oxide) layer (4nm + 1nm) to form the capacitor dielectric between the polysilicon and the substrate (Fig. 4e). Cobalt silicide was used on the gate electrode and the contact side of the transistor.
The silicide and n+ source/drain implant was masked from the capacitor side by the extra layers shown in Fig. 4c; see the logic transistor in Fig. 4d for comparison. The extra sidewall spacers would allow a different S/D implant structure between the gate and the capacitor, probably to minimize leakage.
 Figure 5. Plan-view SEM image of wordlines at polysilicon level. |
The DRAM array itself appeared to use relaxed design rules, since the M1 half-pitch was ~130nm. This caused some confusion when we first looked at the part-was it 90 or 130nm node? The minimum transistor gate length of 45nm cleared that up. The access transistor gate length was ~150nm, narrowing to ~80nm when passing adjacent cells. (In Fig. 5, note the dual sidewall spacers on both sides of the poly track.) The gate oxide was ~ 7nm thick, compared with the ~2nm of the core logic transistors, likely to reduce off-state leakage.
The cell dimensions were 0.53 × 0.38µm, giving a cell area of ~0.2µm2; for comparison, the cell area of a Samsung 90nm commodity DRAM analyzed at the same time was ~0.07µm2.
Looking at this structure, it is obvious that a fair amount of extra processing has to be added, with the associated extra fab and testing costs, but Sony obviously thought it worthwhile to improve the PS2’s performance. The advocates of embedded trench DRAM claim that it has advantages over the stack variety because most of the memory cell processing can be done before the start of the CMOS logic process.
 Figure 6. Xbox 360 GPU e-DRAM. (Courtesy: NEC) |
The NEC e-DRAM part in the X-box 360 was co-packaged with the graphics processor (GPU) designed by ATI, and made by TSMC. It contained 80Mb of memory plus some pixel processing logic (Fig. 6), and was manufactured in NEC’s CB-90M process, using seven levels of copper metal plus a tungsten bitline.
 Figure 7. SEM cross-section of NEC embedded DRAM cells. |
As we said earlier, this part incorporates stack DRAM, featuring capacitor-over-bitline (COB) construction, but unusually with a metal-insulator-metal (MIM) capacitor using a zirconium oxide high-k dielectric layer [2]. Figure 7 is a cross-section of part of a DRAM block showing the cup-shaped capacitors above the bitline, contacting the substrate through a double stack of tungsten plugs. The wordlines are strapped with metal lines at the first copper level.
Again, the memory array used relaxed design rules, with a bitline half-pitch of 140nm, and an access transistor gate length of 130nm, compared with a minimum gate length of ~ 65nm. Cell area is ~0.24µm2.
 Figure 8. Details of NEC e-DRAM capacitor structure. |
Figure 8 shows the details of the cell structure; the capacitor bottom plate was a multilayer titanium nitride (TiN) layer, indicating it was formed by CVD. TEM-EDS analysis confirmed the zirconium oxide (ZrO2) dielectric layer (~10nm) between the bottom plate and the multilayer TiN top plate. There is a tungsten (W) layer overlying the top plate, and if we look closely, we can see that the ZrO2, TiN, and W layers extend beyond the capacitor cup to form a continuous top plate.
Unlike Sony, NEC has not used a silicide mask, but the gate oxide of the access transistors is again thicker than that of the logic devices, at ~5nm vs ~2nm. An unusual feature of this process is the use of silicon-germanium gate electrodes [3]; we found that the Ge content was graded, with twice as much at the base of the gate as at the top. The germanium allows a higher concentration of boron and gives a higher degree of activation in PMOS gates, and enhances arsenic diffusion in NMOS gates, thus reducing gate depletion and improving transistor performance [4].
Again we have considerable complexity added to the process and testing, this time in terms of extra metallization and dielectric layers, and contacts, rather than trench etching and silicide masking. NEC has had embedded DRAM in its process suite from the 350nm node, evolving from polySi/nitride/polySi capacitors to the current MIM version using ZrO2, so they are comfortable using the stack configuration. They did get the design win in the X-box, so it certainly proved its value.
Conversely, Toshiba’s history made it convenient for Sony to use trench technology, so when the needs of the PS2 required integration of the Graphic Synthesizer and the Emotion Engine chips, that was the route taken. In both cases, the e-DRAM enabled a new generation of game consoles-mobile phones come next!
References
- “ASC9: 90nm CMOS Process Technology,” http://www.sony.net/Products/SC-HP/cx_news/vol34/pdf/featuring1.pdf.
- “NEC Electronics Unveils 90nm Embedded DRAM Technology,” http://www.necel.com/news/en/archive/0503/0701.html.
- “Facing the Challenge of CB-90 Development,” http://www.necel.com/en/channel/vol_0002/vol_0002_1.html.
- Kazuya Uejima et al, “Highly Reliable Poly-SiGe/Amorphous-Si Gate CMOS,” IEDM 2000 Technical Digest, pp. 445-448.
DICK JAMES is a 30-year veteran of the semiconductor industry and the senior technology analyst for Chipworks, an Ottawa, Canada-based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, [email protected], www.chipworks.com.