Issue



Reducing USJ-related device variability at 32nm


01/01/2008







EXECUTIVE OVERVIEW

Single-wafer high current implanter designs with diffusion-less annealing flash or laser equipment result in both global and local micro-uniformity variations. These can directly cause local parametric device variation and be especially problematic at the 32nm node. Therefore, design for manufacturing process optimization is required when using spike+msec or msec+spike annealing combinations down to 900°C.

Micro-uniformity variation in ultra-shallow junctions (USJs) caused by device pattern density local loading effects, in combination with microvariation from single-wafer high current implantation and msec (flash or laser) annealers, directly contributes to device variability. These microvariations can be minimized when combined with a diffusion-less low temperature (900-950°C) spike anneal either pre- or post-high temperature (>1250°C) msec annealing.

New noncontact metrology techniques with <0.1mm detection resolution-such as: RL for sheet resistance and junction leakage, and thermal wave for implant dose and after anneal residual implant damage-are very effective in detecting these micro-uniformity variations. Also, molecular dopant species (B18H22, P2, and As2) and high mass dopants (Sb) for p-and n-type SDE and HALO implantation give the highest quality junctions and enhanced dopant activation with diffusion-less annealing techniques. Strain relaxation and high-k/metal gate process integration trade-off issues must also be optimized with these annealing techniques.

For the 32nm node, the industry will target USJ junction depths (X) from a conservative 20nm down to an aggressive 8nm. Achieving high-quality aggressive junctions <10nm will require either diffusion-less or <3nm diffusion annealing techniques. There are numerous annealing options available that are dependent on the high-k/metal gate stack structure and process integration flow such as gate first, gate first but with disposable spacer, gate last, or a hybrid combination (gate 1st and last) including: 1) high temperature msec flash or laser annealing, 2) lower spike annealing temperatures down to 900°C, 3) higher SPE annealing temperatures (>700°C) or 4) combinations of spike+msec annealing or msec+spike annealing (see Fig. 1).


Figure 1. Gate stack, integration, and annealing options for 45nm and 32nm nodes.
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The various dopant activation annealing techniques for minimal dopant diffusion must also be compatible with the strain-Si technique to prevent strain relaxation and degradation of the high-k/metal gate stack structure. Additionally, the implant and annealing USJ process module must be “designed for manufacturing” and not degrade across-wafer device variation [1]. T. Feudel of AMD reported on the effects of annealing technique on device V and I variation, comparing both lamp and non-lamp spike anneals along with spike plus flash or laser msec annealing techniques [2-4]. He reported that lowering the spike temperature from 1085°C to 1025°C reduced device variation, and device performance was improved by adding msec annealing after the low temperature spike anneal [3, 4].

Implant options

Single-wafer HC implanters replaced batch type implanters due to gate poly yield failure, a problem first reported by Y. Kawasaki of Renesas [5]. Each HC implant vendor has a different serial wafer end-station design, including scanning mechanism, resulting in a unique nonuniformity signature caused by local and global variation in implant precision due to dose and angle control. Any variation in localized implant angle will result in asymmetrical transistor, V, gate length variation, and gate delay degradation, as reported by T. Kuroi [6]. Detecting these HC implant localized microvariations requires a metrology tool with a pitch resolution of <0.1mm.


Figure 2. New, high-resolution therma probe of quad-mode implantation and spike annealing: a) contour map, b) DC image mode showing implant and annealing combined signatures, c) AC image mode of implant signature only, and d) diameter line scan of the AC image in c) [7].
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Figure 2 (below) shows results from an improved performance Therma-Probe (TP) metrology system for implantation in the E14 to E16/cm2 dose range [7]. Figure 2a shows full-wafer contour maps of a ribbon beam serial HC implant signature for quad-mode scanning after a spike/RTA anneal. Much of the implantation microvariation is missing and not detected unless a full-wafer DC image mode is used, which reveals both the RTA radial bulls-eye annealing signature superimposed with the implanter quad-mode signature (Fig. 2b). The implant signature can be separated out by using the AC signal only, which clearly reveals the checkerboard pattern caused by the microvariation in the quad-mode implantation (Fig. 2c) [7]. A diameter line scan reveals this variation to be ~31% (Fig. 2d).

The X target for the 45nm node is 12-20nm, and can be achieved using B implant energies in the 200-500eV range with 1000°C spike and msec anneal combinations. However, for the 32nm node, the targeted X is between 8-20nm after anneal, so this drives the B implant energy down to between 100-200eV, which would produce an as-implanted X of 5-6nm if a pre-amorphizing implant (PAI) is used to prevent boron dopant channeling [1]. In this range, conventional high current implanters must use decel-mode, which leads to energy contamination.

The shallow junction requirement places tight constraints on allowable energy contamination, usually <0.1%, limiting decel ratios to <2 to 1. The BF2 option would require energy in the range of 250-500eV, but residual implant defects, end-of-range (EOR) damage, and other adverse effects of fluorine including surface sputtering and retained dose in silicon, makes this option less desirable [1, 8]. However, when using molecular dopant species such as B18H22, the operational energy would be 2-4keV in drift mode, thus avoiding the defect issues with BF2 and PAI+B implants.

Another issue for junctions <10nm is the retained boron dose in silicon after implant and annealing [1]. The Bss (boron solid solubility) activation for flash annealing at >1300°C is >1E20/cm3, provided the retained dose remains >6E14/cm2. With a retained dose of 3E14/cm2, an activation level of only 5E19/cm3 is realized for BF2 with flash annealing; as a result, at low energies, retained dose and total activation levels vary with each dopant species. However, enhanced boron dopant activation by as much as 2× was reported when using B18H22 compared to monomer B or BF2, with or without PAI when using advanced annealing techniques (flash, laser and SPE); molecular dopant species are thus attractive for 32nm node USJ [9-11].

Annealing options

Since the 90nm node, several companies have been using spike+msec flash annealing in production for high performance logic devices, but not for USJ, rather for gate scaling (tox inversion reduction) as first reported by T. Feudel et al. of AMD [3]. Feudel showed that the FEOL roadmap will transition from spike+msec annealing at 65nm node to msec only at the 45nm node and beyond [2], but I believe this may now be delayed until the 32nm node because different flash equipment results in different dopant activation levels and micro-uniformity variation with and without pre-amorphizing implants. Differences have also been reported when using different laser annealing equipment as well [11, 12]. These findings explain the differences in dopant activation for B18H22 (9E19/cm3 vs. 1.7E20/cm3) reported by Borland when comparing two different flash annealing equipment vendors [11].

For arsenic n-type dopant, S. Kato et al. of Selete reported no difference with or without Ge-PAI for different flash annealing power settings. Additionally, antimony dopant was better than arsenic and phosphorus for both flash and SPE annealing [12, 13]. Similar independent results were reported by A. Mineji, comparing As, As2, P2 and Sb [10]. P2 was best with flash annealing, while Sb was second best. When SPE was used, Sb had the highest dopant activation level.


Figure 3. Ge-PAI with SPE or laser annealing shows degradation in junction leakage current determined by RsL measurements [9].
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However, using Ge-PAI can lead to residual EOR damage with diffusion-less annealing, and therefore, several orders of magnitude degradation in junction leakage current as detected by RL metrology (Fig. 3) [9]. Therefore, high quality diffusion-less junctions can be realized with B18H22, which was also verified on pMOS devices with narrow gate lengths (L) down to 27nm that were fabricated with laser annealing as just reported by K. Yako et al. of NEC [14].


Figure 4. Excellent pMOS a) device short channel effect and b) junction leakage current using B18H22 without PAI [14].
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The pMOS V roll-off short channel effects (SCE) for gate lengths down to 27nm are shown in Fig. 4a; junction leakage is shown in Fig. 4b [14]. Excellent SCE effects are seen for both Ge-PAI+B and B18H22, but a two orders of magnitude degradation in junction leakage current was observed with Ge-PAI+B due to residual EOR damage, so the best laser annealing p+ junctions and scaled pMOS devices could only be achieved with B18H22, which is self-amorphizing, but without EOR damage [9].

It is also important to know the msec annealer signature, which can also contribute to both global and micro-localized device variation [15-17]. When only a flash annealing is done, the global wafer variation of 23.6% and local peak-to-peak variation of 3.7% can be detected; with photoluminescence metrology, however, by adding a 900°C spike before or after the flash anneal, the global variation can be reduced to 7.1% and the local variation reduced to 1.1%, with the Xe-lamp pattern signature being eliminated [15]. From the RL metrology measurements, the global variation for the flash-only lamp annealing was detected to be 8% and local peak-to-peak was 1.5% in sheet resistance [17]. Similar effects have also been seen for laser annealing when using a pre- or post-spike annealing step down to 900°C to eliminate the laser overlap stitching pattern signature.


Figure 5. Localized 0.8mm microvariation in sheet resistance for laser annealing [18].
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Direct correlation of these microvariations (that are measured electrically by sheet resistance) to the device variation was reported by T. Hoffmann, et al. of IMEC for laser annealing. In the IMEC study, they detected an R local variation of ~7% due to the laser annealing stitching/overlap pattern effects and localized heating variation (Fig. 5) with a 0.8mm peak-to-peak variation [18]. They then measured long channel V variation, which was found to be ~7% (Fig. 6); with this observation, IMEC reported for the first time a 1:1 correlation between localized R variation to long channel V variation.


Figure 6. Long channel Vt variation with laser annealing for nMOS and pMOS devices [18].
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An area of much debate is whether to do spike annealing first, or msec annealing first. At the May 2007 ECS meeting, T. Feudel reported a spike first+msec annealing for 65nm node production with no degradation in gate oxide [4]. That same week, at the INSIGHTS May 2007 meeting, S. Paul of Mattson reported flash first followed by spike annealing results in deeper junctions than spike first followed by flash annealing. Paul also reported that the spike+flash resulted in higher dopant activation than flash+spike annealing sequence [19].

In another paper at INSIGHTS, as well as at the IWJT June 2007 meeting, IMEC reported gate oxide degradation with spike+DSA laser annealing compared to a DSA+spike annealing sequence [18]. C. Nieh of TSMC also reported better Ge+BF2 dopant activation for a msec+spike vs. spike+msec annealing sequence [20]. S. Endo of Renesas at the IWJT June 2007 meeting also reported LSA laser first followed by spike, was better [21]. However, those using laser annealing first followed by spike also reported the need to do a second laser anneal after the spike/RTA anneal to reactivate the dopant (i.e., a total of two laser annealing steps: msec+spike/RTA+msec).

Strain-Si integration

There are a number of different methods to induce localized tensile and compressive strain in the device channel region for mobility enhancement including: 1) CVD stress liners (tensile for nMOS and compressive for pMOS), 2) stress memorization technique, 3) eSiGe S/D for pMOS, 4) eSiC S/D for nMOS, 5) hybrid-oriented substrate, and 6) STI. However, dislocation formation and strain relaxation with the introduction of msec laser and flash annealing has been observed for SiGe. J. Hoyt of MIT reported LSA laser annealing at a temperature of 1000°C reduced mobility by 25% and at 1100°C by 50% [22]. Similarly, for DSA laser annealing Hoffmann reported10-17% mobility degradation [18]. The trade-off is dopant activation versus strain relaxation. Also, an alternative to eSiC SEG is to use C implantation as reported by Liu of IBM [23] or cluster carbon molecular dopant species as reported by Li-Fatou et al. of TI [24], where they reported up to 100% substitutional carbon.

Conclusion

For the 32nm node, the highest quality junctions with the highest activation are seen when using molecular dopant species or high mass dopant species, such as B18H22, As2, P2 or Sb. However, the retained dose may limit the activation level. Single-wafer high current implanter designs with diffusion-less annealing flash or laser equipment result in both global and local micro-uniformity variations that can directly cause device local parametric variation. Thus, design for manufacturing process optimization is required when using spike+msec or msec+spike annealing combinations down to 900°C. Strain-Si relaxation effects with msec annealing must be minimized, as well as high-k/metal gate degradation effects. Improved and new noncontact metrology techniques with resolution down to <0.1mm will be critical to improve across-wafer uniformity and reduce device variation for “design for manufacturing.”

References

  1. J. Borland, “Process Variability Reduction for Gate Doping and USJs,” Semiconductor International, p. 49, Dec. 2006.
  2. T. Feudel, presentation material at SEMICON/Europe March 2005.
  3. T. Feudel et al., “Process Integration Issues with Spike, Laser, and Flash Anneal Implementation for 90 and 65nm Technologies,” 14th International Conference on Advanced Thermal Processing (RTP), p. 73, 2006.
  4. T. Feudel et al., presentation material “Reduced Parametric Fluctuation with Laser and Flash Lamp Anneal for 65nm Volume Production,” Electrochemical Society Meeting, abstract #599, May 2007.
  5. Y. Kawasaki et al., “The Collapse of Gate Electrode in High Current Implantation of Batch Type,” IWJT 2004, p. 39.
  6. . T. Kuroi et al., “Ultra-shallow Junction Formation for 45nm Node and Beyond,” USJ 2005, p. 4.
  7. A. Salnik, “Advanced Implant and Junction Metrology for 45nm and Beyond,” KLA-Tencor presentation material at SEMICON West 2007/West Coast Junction Users Group meeting.
  8. J. Borland et al., “High Dopant Activation and Low Damage p+USJ Formation,” IIT 2006.
  9. J. Borland et al., “45nm Node p+USJ Formation with High-Dopant Activation and Low Damage,” IWJT 2006, p. 4.
  10. A. Mineji et al., “Molecular Dopants and High-Mass Dopants For HALO and Extension Implantation,” IWJT 2007, paper S4-8.
  11. J. Borland, “Device Variability and Implant & Annealing Options Limited by Strain-Si and High-k Gate Process Integration,” J.O.B. Technologies presentation material, SEMICON West 2007/West Coast Junction Users Group meeting.
  12. H. Kiyama, “Applications of Flash Lamp Annealing,” Dai Nippon Screen presentation material, ibid.

  1. S. Kato et al., IWJT 2007, p. 143.
  2. K. Yako et al., “Reduction of Junction Leakage by B18H22 Cluster Ion Implantation and Laser Annealing,” Japan Society of Applied Physics, 68th Autumn Meeting, Sept. 4-8, 2007.
  3. J. Borland et al., “Improving Junction Uniformity and Quality with Optimized Diffusion-less Annealing,” IWJT 2007, paper S4-7.
  4. C. Raymond, “Photoluminescence Metrology for Global Wafer and Micro Implant and Anneal Uniformity,” Nanometrics presentation material at SEMICON West 2007/West Coast Junction Users Group meeting.
  5. J. Halim, Frontier, private communications.
  6. T. Hoffmann et al., “Laser Annealed Junctions: Process Integration Sequence Optimization for Advanced CMOS Technologies,” IWJT 2007, p. 137.
  7. S. Paul et al., INSIGHTS Meeting May 2007.
  8. C. Nieh et al., IEEE EDL, Vol. 27, No. 12, p. 969, Dec. 2006.
  9. S. Endo et al., IWJT Meeting June 2007, p. 135, June 2007.
  10. J. Hoyt, presentation material of MRS Spring 2007 meeting, April 2007.
  11. Y. Liu et al., VLSI Sym. 2007, paper 4A-2.
  12. A. Li-Fatou et al., Fall Oct. 2007 ECS meeting, Washington, DC, abs. #1305.

John Borland received his BS and MS from MIT and is founder/president of J.O.B. Technologies, 98-1204 Kuawa St., Aiea, Hawaii 96701 United States; e-mail [email protected].