Eliminating micro-cracks, crystal dislocations with single-wafer surface conditioning
01/01/2008
EXECUTIVE OVERVIEW
Stacked-die-attach package applications require backside metal deposition for device contact within the package. This needs an optimized surface for backside metal adhesion. Wet chemical etching can provide a uniform, customized backside wafer surface roughness between 0.44 and 1.77μm.
The need for backside metal adhesion and solder contact for ultra-thin, discrete, high-power semiconductor devices has increased significantly over the past several years. To provide an optimized backside metal adhesion contact to the silicon wafer’s surface, a tailored backside surface is required for the specific silicon type, resistivity, and dopant level, as well as the metal or metal stack being deposited. This surface is critical so that the backside metal layer does not crack or peel from the under-package stress and heat, and result in yield or performance loss.
The demand for thinner substrates in consumer products requires that a semiconductor wafer be thinned to less than 150μm. The most common method of wafer thinning is the mechanical backgrinding process. Though backgrinding provides a relatively low cost-of-ownership, it leaves a non-uniform surface containing micro-cracks and crystal dislocations within the silicon, creating stress points and weak adhesion points for backside metallization. The process can produce a backside wafer surface acceptable for some backside metal adhesion processes, though it depends on the final grinding wheel used, and the package thickness requirements of the die. Because backgrinding leaves a silicon wafer vastly rigid, it does not allow for wafer flexibility. As a result, the wafer and backside metallization layer can crack. A fine grinding wheel, such as a 2000-grit finishing wheel, is used more frequently to minimize micro-cracks from the coarse backgrinding process. However, the surface left behind is not optimized for most metal-adhesion processes due to the texture and roughness values. Furthermore, grinding wheels degrade with use and the degradation is never constant. Thus, repeatability is another key problem.
A common method for eliminating micro-cracks and crystal dislocations is single-wafer wet-chemical etching, which uses a combination of inorganic chemicals to selectively etch away the damage induced into the silicon substrate. Wet chemical etching can provide a uniform, customized backside wafer surface roughness between 0.44 and 1.77μm. These surfaces can be achieved by using different chemical etchant formulations and temperatures to provide optimized backside metal adhesion. Because the surface is chemically treated, the backgrind-induced damage is removed by the chemistry while creating a roughened surface optimum for backside metallization. It is also possible to form extremely smooth silicon surfaces by altering the chemical and process parameters.
Experimental and results
All tests within this experiment were conducted with mechanical-grade P 100, 0-50Ωcm, boron-doped, 300mm silicon wafer substrates, initially background to 200μm with an “in-feed” grinder and 2000-grit final grinding wheel. The silicon wafers were then chemically etched on a spin processor. A profilometer with a 0.1-μm stylus measured backside surface roughness. All scans with the profiler measured 0.05mm in length, with a downward contact stylus force of 10mg. A focused ion beam scanning electron microscope (FIB-SEM) captures the surface detail of the roughness produced [1].
 Stacked-die-attach package applications require backside metal deposition on an optimized surface for device contact within the package. |
Figure 1 shows a clear “pinwheel” type pattern across the entire wafer’s backside surface, formed by elongated grind lines from the center to the edge of the wafer. This is indicative of the movement of the grinding wheel across the wafer surface and leads to inherent stress in the wafer. Surface roughness is characterized by total indicator run-out (TIR). The TIR is calculated by the maximum peak height value minus the minimum peak value within the length of the line scan. Roughness average (Ra) values were also calculated. This value represents the roughness average within the length of the line scan. Considerable variation is evident in the surface localized uniformities. Variation in the surface is needed for optimized metal adhesion, as it provides additional surface area.
 Figure 1. SEM and roughness data images of backside of a wafer processed by in-feed backgrinding. |
However, the silicon particles, micro-cracks, and surface non-uniformity that remain provide weak adhesion points. The profilometry data illustrates the distances from the peaks of the silicon damage to the lower surface levels where micro-cracks initiate into the remaining bulk silicon surface. The x axis of the graph represents the scan length, while the y axis represents the surface roughness scale. This wafer’s surface roughness varied considerably from center to edge. Measurements taken in the very center of the wafer measured 450.19nm TIR with a 76.28nm Ra. When measured in the middle area of the wafer between the center and the edge, the values calculated were 500.17nm TIR with an Ra value of 78.25nm. Alternatively, when measured 20mm from the edge of the wafer, the TIR value reached 993.06nm; the Ra value was 207.48nm. This demonstrates that the surface area of a background wafer more than doubled in TIR values while nearly tripling Ra values from center to edge. Such surface non-uniformity could create issues with metal adhesion and metal layer uniformity, and demonstrates the inconsistency of the backgrind approach.
 Figure 2. SEM and roughness data images of backside wafer processed with TE1 for 60 seconds at 55°C. |
To compare the effect of grinding alone with grinding and wet etching, a set of chemical etching tests were performed. After grinding to 200μm, a proprietary wet chemical blend texture etch (TE1) was used [1]. The chemical process was run for 60 seconds at 55°C and was based on an established best known method (BKM) that provides a matte, roughened surface finish, optimum for backside metal adhesion. As the chemical media is dispensed, oxidation and out-gassing occur while the silicon is etched, creating a roughened topography of silicon peaks and valleys on the wafer surface (Fig. 2). The wafer’s surface roughness was then measured, revealing values of 954.75nm TIR and 157.45nm Ra with <10% non-uniformity surface roughness from center to edge. The difference in surface non-uniformity, roughness, and adhesion potential is enormous relative to a wafer that is background alone.
 Figure 3. SEM and roughness data images of backside wafer single-side polished (SSP). |
A second set of test wafers were processed with a similar mixture to the TE1 tests, but the chemical formulation was modified. The second chemistry tested, TE2, has a similar component make-up as TE1, with concentration of the oxidizing chemical increased relative to that of TE1. In these experiments the wafers were processed in this second mixture for 15 seconds at 25°C. The lower temperature was chosen to minimize out-gassing, which in turn helps minimize surface roughness. The purpose of these tests was to prepare a wafer surface on a thinned wafer that has a similar surface roughness to the backside of a conventional single-sided polish (SSP) wafer. As a reference, the profile of the backside of a 200mm unprocessed wafer was measured (Fig. 3). The results calculated a TIR value of 587.85nm and an Ra value of 150.68nm. The initial wafers processed with TE2 demonstrated that the wafer’s surface finish was considerably different than the conventional SSP wafer backside surface references, and different from the results seen with the TE1 chemistry. The results are due to a decrease in the rate of chemical reactivity on the wafer surface associated with changing the oxidizer concentration and process temperature. While still providing a textured, rough, damage-free surface following mechanical backgrinding, the TE2 chemistry provided a surface finish that could be used for backside metallization. The results from the roughness metrology calculated a 463.96nm TIR value and 64.99nm Ra. By increasing the process time to 20 seconds, it was possible to achieve roughness values closer to the SSP reference wafer with 613.29nm TIR and 108.9nm Ra (Fig. 4).
 Figure 4. SEM and roughness data images of backside wafer processed with TE2 for 20 seconds at 25°C. |
Further tests were performed using TE2 with process time increased to 60 seconds. This resulted in a matte surface finish similar to the second set of tests, but with a dramatic increase in roughness in the silicon surface. The surface roughness was increased by a factor of nearly 3 over the initial process at 20 seconds. The SEM and surface profile in Fig. 5 have a calculated value of 1.77μm TIR with 280.68nm Ra.
 Figure 5. SEM and roughness data images of backside wafer processed with TE2 for 60 seconds at 25°C. |
Conclusion
Wafer backside surfaces can be selectively tailored with a single roughness chemistry using a single-wafer wet process, which allows surfaces to be optimized for different backside metallization processes. With minor adjustments to the amount of oxidizing agent in the chemical etchant blend and modification of the process conditions used, it is possible to control the condition of the surface (see table). Furthermore, wet chemical etching removes the backside silicon damage caused by mechanical backgrinding processes, thereby increasing wafer and die strength while providing more uniform surface roughness values across the wafer.
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References
1. Tools and chemistries used included an SEZ 300mm spin processor, a KLA-Tencor P2 long scan profilometer, an FEI Expedia 1265 dual beam scanning electron microscope, and Honeywell’s Texture Etch.
Contact the author for a complete list of references.
SCOTT DREWS, research project coordinator, may be contacted at SEZ America Inc., 4829 S. 38th St., Phoenix, AZ 85040 USA; ph 602/437-5050; e-mail [email protected].
This article was originally published in the August/September 2007 issue of sister publication Advanced Packaging (www.apmag.com).