Issue



Thermal processing issues for 22nm node junction scaling


08/01/2009







Junction scaling for 22nm node planar and FinFET CMOS requires low energy implantation, but the surface oxide thickness will determine the energy (>83eV) and dose. Engineering the surface amorphous layer maximizes dopant activation, and reduces implant damage and junction leakage with sub-melt laser or flash lamp annealing. The annealing process and equipment must be optimized to prevent strain relaxation, high-k/metal gate stack failure and wafer breakage.

John Borland, J.O.B. Technologies, Aiea, HI; Susan Felch, Los Altos Hills, CA; Zhinmin Wan, AIBT, San Jose, CA; Masayasu Tanjyo, Nissin Ion Equipment, Kyoto, Japan; Temel Buyuklimanli, EAG, Windsor, NJ

A main focus with junction scaling for the 22nm node is defect reduction and lowering junction leakage, especially for system on a chip (SOC) with logic embedded memory devices. There are several ways to reduce residual implant damage from an implant and annealing perspective. Low damage implantation can be realized by: 1) higher implant beam current or dose rate; 2) lower implant wafer temperature (cryo-implantation) 0??C to -160??C by using chilled water or liquid nitrogen wafer cooling; 3) using molecular dopants such as B18H22, B36H44, As4 or P4; and 4) using lower dose heavier ions for pre-amorphizing implant (PAI) such as In, Sb, or Xe. These techniques improve self-amorphization, lower critical implant doses for amorphization and smooth amorphous interfaces thereby reducing end of range (EOR) and residual implant damage while enhancing dopant activation with msec anneal (MSA). Higher MSA peak temperature and/or pre-/post-MSA diffusion-less spike/RTA at <900??C leads to stable defects and a reduction in residual implant damage, improving junction leakage.

Planar CMOS doping

At the 22nm node, dopant diffusion must be minimal to achieve the targeted junction depth (Xj) between 6 and 12nm. The three options for doping these ultra-shallow junctions (USJ) are: 1) lower energy beam-line implantation without deceleration energy contamination, 2) higher energy beam-line implantation using molecular dopants, or 3) plasma implantation. For p+ USJ, monomer B >83eV or BF2 >450eV implant energy with no dopant channeling, and for maximum dopant activation and low leakage Ge-PAI >3keV, Xe-PAI >5keV, or In-PAI >5keV. Using B18H22 (>2keV) or B36H44 (>4keV) molecular dopants avoids the need for PAI due to enhanced self-amorphization, but retained dose is only 75%; 55% with BF2. Figure 1 shows high-depth resolution PCOR-SIMS of 100eV B equivalent at 1E15/cm2 dose for B18H22 and B36H44 implantation into crystalline and amorphous silicon using the Nissin Claris molecular dopant implanter [1]. Note that the difference in Xj at 5E18/cm3 with and without Ge-PAI is only 0.4nm (Xj=7.2nm versus 6.8nm) due to the self-amorphization effects of molecular dopants.


Figure 1. B dopant profile and surface oxide profile using PCOR-SIMS for B18H22 and B36H44 at 100eV equivalent and 1E15/cm2 total dose [1].
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With PCOR-SIMS, the presence of a 1.2nm-thick surface oxide was detected as shown in Fig.1, so the corrected electrical B junction depths are 6.0 and 5.6nm, which becomes critical for process and device simulation modeling when the surface oxide can be 20-30% of the physical implant depth and contain 40-60% of the total dose. Without this surface oxide, the implant energy would need to be reduced from 100eV to 83eV to achieve an Xj<6nm. With BF3 plasma implantation (>250V), an amorphous layer (PAI) is still required to reduce channeling and enhance dopant activation, but a major problem is surface sputtering and retained dose of <11% [2]. This can be improved if using B2H6+He plasma implant process. For n+ extension switching from arsenic (As) to phosphorus (P) or antimony (Sb) at 500eV or 1.7keV, respectively, improves dopant activation with MSA, and the lateral straggle with P improves gate overlap with 0?? tilt angle, avoiding the need for tilted nSDE implantation when using As or Sb dopant species.


Figure 2. B dopant profile and surface oxide profile using PCOR-SIMS for Ge+BF2.
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Achieving shallow as-implanted Xj does not guarantee USJ after MSA, where as much as 4nm of dopant diffusion can occur due to diffusion during amorphous layer regrowth, especially when using PAI. PCOR-SIMS of B and surface oxide for 10keV Ge-PAI at 5E14/cm2 and 500eV BF2 at 1E15/cm2 implantation on the AIBT iPulsar single wafer high-current implanter followed by MSA on the Applied Materials DSA sub-melt laser annealer at 1175??C, 1225??C, 1275??C, and 1325??C is shown in Fig.2. Compared to the no-annealed reference, 1175??C anneal resulted in 2.4nm of B dopant movement; this increases to 3.2nm at 1225??C, 4.0nm at 1275??C, and 4.2nm at 1325??C. The sheet resistances (Rs) reported in ref. 2 were 2000 Ω/sq. for 1175??C and 1225??C, 1800 Ω/sq. for 1275??C and 1400 Ω/sq. for 1325??C. The corrected electrical Xj was determined by subtracting out the 1.8nm surface oxide thickness detected by PCOR-SIMS, so the calculated B dopant activation level limited by boron solid solubility (Bss) varied from 6 to 8E19/cm3 as shown in the Rs versus Xj chart of Fig. 3.


Figure 3. Rs versus Xj chart for monomer B and BF2 p+ USJ.
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Without Ge-PAI, the corrected Xj for BF2 with 1325??C MSA was 6.6nm for a Bss=4E19/cm3 whereas with 1175??C MSA, Xj was 5.8nm for a Bss=3E19/cm3 (Fig.3). Due to the lower retained dose with BF2 (5.5E14/cm2) the maximum dopant activation was much lower than the monomer B results. The surface oxide for all the monomer B implants was thicker at 2.3nm based on PCOR-SIMS and verified by XPS and X-TEM [2]. The corrected electrical Xj after the 1325??C MSA for B was 6.9nm, Ge+B was 10.5nm, and Xe+B was 9.7nm. The Bss values for the monomer B implants shown in Fig.3 are: 1) Bss=5E19/cm3 for 1175??C and 1225??C MSA, 2) increases to Bss=1.2E20/cm3 for 1325??C MSA, 3) increases to Bss=1.3E20/cm3 with Ge-PAI at 1325??C MSA, and 4) up to Bss=3.5E20/cm3 with Xe-PAI at 1325??C MSA.


Figure 4. Laser annealing temperature effects on junction leakage current.
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Reducing residual implant damage or EOR defects and junction leakage current can also be achieved by using higher MSA temperatures, additional pre- or post-MSA 900??C spike/RTA or low damage PAI as shown in Fig.4. Similar RsL leakage results for monomer B and BF2 were reported in ref. 3. A 14???16nm deep amorphous layer is created by the Ge (10keV), Xe (14keV) and In (14keV) PAI. The lowest junction leakage <5E-8A/cm2 is realized for In-PAI, while for Ge-PAI the leakage is in the E-5A/cm2 level for 1175??C MSA temperature and improves to E-8A/cm2 level for >1275??C. Xe-PAI behaves differently; the leakage level is E-4A/cm2 for all MSA temperatures but a pre-MSA 900??C spike/RTA improves leakage to E-6A/cm2 level. Reducing the Xe-PAI energy to 5keV will reduce the amorphous depth to <6nm (Xj-EOR=+nm) and leakage to <E-7A/cm2 level as reported by Borland et al. using Si-PAI [4], Ge-PAI [5], and Xe-PAI [3].

FinFET CMOS doping

Both SOI and bulk FinFET structures are doped using high tilt implantation. However, retained dose, one of the concerns with high tilt implantation, is affected by dose loss due to the cosine angle effect at higher tilt angles and sputter or reflection dose limit at lower implant energies and higher doses. Plasma implantation has been studied as an alternative to improve conformal chemical doping, but recent results have shown to be not truly conformal with severe FinFET erosion [6]. However, beam-line molecular dopant implantation up to 60?? tilt with Flash MSA was reported to enhance dopant activation [7]. They observed that monomer B at 45?? tilt with retained dose >1.1E15/cm2 had the lowest electrical activation level (Bss=2.8E19/cm3) when using MSA (Fig. 5), while B18H22 at a tilt of 60?? had a retained dose of 5.5E14/cm2 but the highest dopant electrical activation level (Bss=1.1E20/cm3). Therefore, conformality and highest electrical dopant activation level are more important for 3D structures when using MSA than the conformal retained chemical dopant level, and the best results were realized using B18H22 molecular dopant compared to monomer B and BF2 [7].


Figure 5. Effects of Xj at 60?? tilt angle for BF2 and B18H22 and 45?? for B on a) PCOR-SIMS retained dose and b) Bss dopant activation level.
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MSA process and equipment design issues

MSA from 1100?? to 1350??C enhances USJ dopant activation, especially when PAI or a self-amorphous layer is present as shown in Figs.3 and 5. But these processes do not completely eliminate unstable residual implant damage unless >1300??C, or they are in combination with a low-temperature 900??C spike/RTA annealing step as shown in Fig. 4 (which shows improvement in junction leakage current).

At the 45nm node, most logic and foundry companies introduced either Flash lamp or sub-melt laser MSA in combination with >1020??C spike/RTA in manufacturing. Due to wafer thermal shock, a continuing concern with Flash annealing is wafer slip, warpage, and breakage, requiring special hardware, limited process space, and lots of confidential know-how to avoid it. Wafer breakage can also occur with laser annealing, though not as commonly. However, with laser annealing, localized hot spots (+50??C) can occur [8], causing poly-Si line breakage. The drive to higher MSA peak temperatures for certain benefits and the need for lower MSA peak temperatures for others necessitate a compromise solution that will be different for each customer’s confidential implementation.  

With Flash lamp MSA, the dwell times are 1???50msec, but if the dwell time is too short, incomplete recrystallization will occur leaving a shallow surface amorphous layer [9]. The number one concern with Flash MSA is wafer breakage caused by thermal shock dependent on substrate type (p/p+ epi wafer, hydrogen denuded HAI-wafer, SOI wafer, etc.) and prior wafer edge damage requiring wafer pre-screening. Increasing Flash pre-heat temperature above 450??C before the MSA step minimizes thermal stresses, but can cause complete recrystallization of the amorphous layer before the MSA step and/or TED (transient enhanced diffusion). Using a hot chuck for pre-heating limits the upper temperature to <650??C, and therefore the peak MSA temperature to <1250??C to avoid wafer breakage. With bottom lamp pre-heating the lower limit is >650??C and peak MSA can be >1350??C before wafer breakage. Flash lamp heating non-uniformities and pattern density effects have been reported to cause ??60??C temperature variation across the wafer [8].

With sub-melt laser MSA, dwell times from 100??sec to 1msec are used and shorter dwell time minimizes localized stress. Wafer warpage/slip due to thermal stresses can lead to lithography overlay problems [10]. Similar to Flash MSA, higher wafer pre-heat temperatures reduce thermal stresses, but 400??C is typical to avoid recrystallization of amorphous layers. With laser MSA the overlap stitching pattern can lead to local non-uniformities [5].

Laser wavelength effects and Brewster angle incidence also influence pattern sensitivity effects, especially with poly and metal lines, requiring some companies to do quad-mode (4?? wafer rotation) for uniform annealing around the gate stack structure. Faster cool-down than Flash, due to additional cooling from cold wafer around laser spot, minimizes diffusion but also causes localized thermal stress.

All MSA techniques use three variables for process optimization: peak temperature, pre-heat temperature, and dwell time. Temperature measurement (with patterns) on this sub-msec time scale with feedback for temperature control is very difficult [10]. Cost-of-ownership (COO) issues include throughput, reliability, and light source lifetime. Integration issues with strain-Si technology and high-k/metal gate stack structures are also concerns. With eSiGe strain technology the Ge content can reduce the surface melting temperature by 200??C, limiting the maximum MSA peak temperature to <1200??C to prevent strain relaxation. Reducing the laser anneal dwell time also helps, as does choosing an implant species that minimizes damage/amorphization in the eSiGe region. With eSiC the opposite is observed: for maximum carbon substitutional (Csub) formation, MSA peak temperature must be >1300??C. Failure of high of high-k/metal gate structures at >1300??C MSA temperatures must be avoided [11].

Conclusion

Scaling CMOS junctions for the 22nm node requires a combination of ultra-low energy beam-line dopant implantation down to 83eV dependent on the surface oxide thickness; self-amorphization or optimized amorphization of the near-surface silicon region, to maximize dopant activation with diffusion-less annealing; and defect stabilization to reduce junction leakage and residual implant damage with diffusion-less msec annealing only, or in combination with a low temperature (<900??C) spike/RTA annealing. These junction scaling techniques can be applied to planar and FinFET CMOS device structures. However, high-temperature msec annealing using Flash lamp or sub-melt laser annealing equipment can cause catastrophic device and wafer yield loss if not carefully optimized.

Acknowledgments

The authors are grateful to Tsutomu Nagayama and Nariaki Hamamoto of Nissin Ion Equipment for support with the B36H44 implants and to Jeremy Zelenko of Applied Materials for support with the DSA laser anneals. Thanks also to Yuen Lim of Frontier Semiconductor for RsL junction leakage measurements.

References

  1. M. Tanjyo, et al., Semicon/China 2009, ISTC/CSTIC 2009, China Semiconductor Technology International Conference, March 19-20, 2009, Shanghai, China, p. 234.
  2. J. Borland, Semiconductor International, Dec. 2006, p.49.
  3. J. Borland, et al., Insights-2009 meeting April 26-29, 2009, Napa,CA, p.25.
  4. J. Borland, T. Matsuda, K. Sakamoto, Solid State Technology, June 2002, p. 83.
  5. J. Borland, Y. Kawasaki, J. Halim, B. Chung, Solid State Technology, July 2008, p. 38.
  6. W. Vandervorst et al., IIT-2008, June 2008, p. 449.
  7. J. Borland, M. Tanjyo, T. Nagayama, N. Hamamoto, Insights-2009 meeting April 26-29, 2009, Napa, CA, p. 352.
  8. T. Kubo, T. Sukegawa, M. Kase, IEEE/RTP 2008 meeting, Sept. 30-Oct. 3, 2008, Las Vegas, NV, p. 195.
  9. H. Kiyama, T. Kusuda, S. Kato, T. Aoyama, extended abstracts IWJT-2008, May 15-16, 2008 Shanghai, China, p.206.
  10. Y. Wang, J. Hebb, D. Owen, A. Hawryluk, Semiconductor International, Dec. 2008, p. 22.
  11. O. Gluschenkov et al., presentation material, Insight-2009, April 27-29, 2009, Napa, CA, p.12.

John Borland received his BS and MS from MIT and is founder of J.O.B. Technologies, 98-1204 Kuawa St., Aiea, HI 96701 USA; [email protected].

Susan Felch received her AB in physics from Dartmouth College and her PhD in physics from Stanford U. She is a consultant specializing in plasma doping, ion implantation, and advanced annealing.

Zhinmin Wan, received his BS in physics from China University of Science and Technology in Hefei, China and his MS and PhD degrees in physics from State University of New York at Stony Brook. He is VP of engineering at Advanced Ion Beam Technology (AIBT), San Jose, CA USA.

Masayasu Tanjyo received his B. Eng and M. Eng degrees from Hokkaido U. and PhD in plasma physics from Nagoya U. and is expert manager at Nissin Ion Equipment, Kyoto, Japan.

Temel Buyuklimanli received his BS in physics from the Middle East U. in Ankara, Turkey, his MS and PhD degrees in physics and material science & engineering from the U. of Florida. He is director of the quadrople SIMS group at EAG, Windsor, NJ USA.