Holistic efficiency optimization: how to help in a downturn
03/01/2009
Martin van den Brink, ASML, Veldhoven, Netherlands
The industry is in another cyclical downturn. No one knows the depth or length of this cycle, but one thing is certain — manufacturing efficiency will be important. Since new fab spending is being cut back, getting the most out of existing fabs becomes critical, especially when the upturn begins. Efficiency can be accomplished by fitting more die per wafer, and also by getting more wafers out of the fab, that is, by increasing the throughput of the fab. Finally, higher efficiency can be achieved by increasing the yield of the fab giving more good die out.
Obtaining more die/wafer has traditionally been achieved in two ways. One is by increasing the wafer size; as the current 300mm wafer size is unlikely to increase in the next few years, this avenue is not available. The recent closures of 200mm commodity fabs point to the importance of this factor. The second is to follow Moore’s Law and shrink the critical dimensions of the chip. Scaling has progressed to the point that new transistor materials are required. These materials have been developed and are being used in leading production.
Patterning scaling has usually been led by improved lithography resolution. The traditional improvements in lithography resolution have been lower bandwidth illumination or larger numerical aperture lens paths. Lower wavelength illumination will be introduced with extreme ultraviolet (EUV), but this is still several years from production. The numerical aperture (NA) for immersion scanners has been increased to 1.35, but further improvement is unlikely. To allow further scaling, a range of other resolution enhancement techniques have been developed that leading vendors are implementing. These techniques, from advanced illumination shaping to radical mask pattern enhancements, require powerful computational modeling (computational lithography) and intimate knowledge of the scanner systems. This combination is allowing the mask designs to be optimized for a given class of lithography systems; needless to say, the better the knowledge of the scanners to be used, the better the design of the mask and the illumination.
In the second area of improving cost efficiency, more wafer throughput for the fab can be accomplished by increasing the speed at which wafers are being processed, especially for the bottleneck processes. Lithography systems are the most expensive in the fab and are used in highly re-entrant wafer flows, with dozens of repetitive uses. For this reason, the fab is usually designed with lithography as the bottleneck process. This means fab throughput is directly linked to scanner throughput. This becomes even more critical as some of the resolution enhancement techniques used requires doubling the lithography steps per layer. The newest scanners are constantly improving throughput while delivering ever tighter positioning accuracy.
Another factor in fab throughput is scheduling efficiency, which has traditionally been restricted by scanner variation. However, by combining computational lithography modeling with advanced adjustments of the individual scanners, a new level of scanner matching is allowed. The matching is no longer limited to a few representative patterns but can be optimized over the entire chip for each critical layer and design. Importantly, the matching can also be extended across scanner families. All this opens up the scanner selection criteria for fab scheduling and therefore improves fab throughput. This level of optimization can only be achieved with a holistic view of the lithography, using computational lithography as the bridge between the actual manufacturing systems in the fab and the incoming designs.
Higher yield is always a direct contributor to fab efficiency. It is difficult, however, to precisely link any yield movement to individual processes unless there are gross failures in the tools. Nonetheless, the holistic approach leads to broader process windows by simultaneously optimizing the illumination shape and the mask patterns. Up to 20% increases are not uncommon. Computational lithography enhanced matching has typically shown improvements in matching performance of 30% to 70%. All these contribute to improved yield.
This downturn will test the industry’s ability to squeeze more efficiency from manufacturing. By tying together more elements of design and manufacturing through computational modeling, a large contribution is produced.
Martin van den Brink, is Executive Vice President, Marketing and Technology at ASML, De Run 6501, Veldhoven; Netherlands; ph. +31 40 268 3521; email [email protected].