Ion implant: a new enabler for 32nm and 22nm devices

03/01/2009

James Kawski, Mark Merrill, Varian Semiconductor Equipment Associates Inc., Gloucester, MA USA

Over the years, suppliers of ion implant tools have competed mostly on productivity and cost of ownership differentiation. The challenges associated with the migration to 32nm and 22nm have opened up new opportunities and ion implant is one technology that is on track to enable chip manufacturing at future technology nodes.

In the beginning, ion implant was enabling. VLSI circuits could not have been fabricated were it not for the inherent precision of ion implant. Specifically, ion implant enabled accurate threshold adjust voltages on MOSFETs. This enabled low-power CMOS logic and, after a dozen or so technology nodes, our industry has changed the world.

Implant brought three capabilities to the table: uniform dopant distribution across the surface of the wafer, accurate control of the dopant profile and depth, and highly accurate dopant density. These capabilities facilitated dopant profile engineering that was essential for the advent of early CMOS. Without implant, CMOS wouldn’t have seen rapid growth and expansion, or profoundly impacted our lives.¹

Historically, implant has had to be highly precise and productive. Unlike deposition, etch, or lithography, implant has never been a consistent or recent enabler of sequential technology nodes. After its initial contribution, it is traditionally extendable over multiple nodes. This created an environment where, for years, implant suppliers competed on productivity and cost. For example, mechanically limited implant throughputs have increased from ˜200 wafers per hour (wph) in 2004 to over 500 wph today. What are the challenges that enable new shrinks, and is implant innovation required?

Technical barriers

The technical barriers for shrinking devices are becoming extremely complicated. The ultra-shallow junctions and short channels in 32nm and 22nm transistor node development are becoming just a few atoms wide. Implant inherently disturbs atoms, resulting in crystal damage that, in turn, creates unacceptable device leakage that will increase a given chip’s power consumption.

We can list a few of these challenges from an implant perspective:

1. Leakage of low power transistors (damage in the crystal lattice);
2. Shallow junction profiles (accurate placement of dopant profile);
3. Shrinking wells and device isolation (accurate placement of dopant due to angle);
4. Process simplification (cost).

   Leakage

   As devices shrink, effective gate lengths approach the depletion widths of the source and drain junctions. These types of scaling issues induce a variety of short channel effects (SCE) that impact transistor leakage and performance. For the future 32nm and 22nm nodes, implant is uniquely positioned to neutralize these issues through damage engineering applications. Device scaling requires a continuous reduction in junction depths, which are on the order of 10nm at the 32nm node. This scaling is accomplished with an equally continuous reduction in thermal budget.

   Click here to enlarge image

   The most recent development is the introduction of millisecond annealing techniques such as laser or flash annealing. However, such advanced annealing techniques are not able to completely remove the damage from the implant step, while devices become more sensitive to it. To address this dilemma, a method of precision damage engineering was developed. This enhanced amorphization technique lowers the amorphization threshold of the Si substrate, resulting in a more abrupt implant profile, enhanced amorphization by the implant, and a subsequent lack of residual damage post-anneal (referred to as PTC-II).

   Figure 1. End of range (EOR) damage is reduced compared to traditional pre-amorphization implant (PAI) using PTC-II damage engineering process with implant.Click here to enlarge image

   Significant work is underway on in situ implant process modifications that minimize defects and their impact on SCEs and leakage. Through VSEA’s PTC-II process, the amorphous region created by implant is increased resulting in a reduction of self-interstitial atoms that are at the origin of end-of-range defects formed after thermal annealing. Figure 1 illustrates the PTC-II process compared to a conventional pre-amorphization implant (PAI). These end-of-range (EOR) defects are responsible for dopant diffusion and activation anomalies as well as leakage. Reduction and/or annihilation of EOR defects via PTC II reduces junction leakage and minimizes dopant diffusion and dopant deactivation mechanisms enabling better junction formation.²

   Shallow junctions

   One of the conventional ways to obtain a shallower junction depth is to reduce the implantation energy. However, this approach has reached an impasse where a further energy reduction will lead to a strong degradation in throughput and uniformity. Therefore, new innovative doping techniques have been researched actively in recent years. Among these techniques is molecular doping, or cluster ion implant, which has emerged as a viable approach in the creation of ultra-shallow junctions with high productivity that is free from energy contamination. The Carborane (C2B10H12, CBH) ion is one such molecular specie that has been considered widely in the industry. Because of the size of the ion and the number of dopant atoms included in the molecule, implants made with CBH typically require a 10?? lower dose and 13?? higher energy.³ CBH is a thermally stable molecule that makes it attractive for ionization in a standard hot cathode ion source, like all other standard dopant ions insuring maximum implanter flexibility and utilization.

   Figure 2. Ion-Ioff characteristics of pMOSFET.Click here to enlarge image

   Because of the size of the CBH molecule, shallow junction implants benefit from self-amorphization which creates a lower sheet resistance for the same junction depth. As illustrated in Figure 2, use of CBH in the formation of shallow low resistance S/D extensions has resulted in a 6% improvement of on-current without any deterioration of SCEs, thereby positively impacting device performance.⁴ CBH appears to be well suited to meet the advanced USJ requirements for 32nm technology and beyond.

   Shrinking geometries and isolation

   As devices shrink so do the deep wells that isolate devices. In prior node transitions this has not been an issue. However, for 32nm and 22nm nodes there is a problem.⁵ To eliminate channeling across the wafer, well implants are usually performed with up to 7° of tilt. High energy implants require a thick photo-resist mask, which shadows any implant that is not normal to the wafer.⁶ Figure 3 shows the shadowing that occurs with a 7° implant. Such an implant may lead to shifts in well boundaries, and poor inter-well isolation.

   Figure 3. Illustration of the shadowing that occurs with non-zero degree implants.Click here to enlarge image

   Lateral device dimensions have decreased faster than well junction depths. Photo-resist thickness has therefore not scaled with device size and the problems due to shadowing have increased. To avoid these problems, high energy implants need to be done at a true 0° angle. It has been shown that a true zero implant cannot be done on conventional batch implanters due to a “cone angle effect“⁶ and that has driven the development of the single wafer high energy ion implanter, which has no cone angle effect.

   Cost

   One constant in ion implant has been the need to push the present boundaries for production-proven cost performance with higher doses at lower energies. In the past two years there has been growth of a new market for these ultra-high dose (UHD) applications. The most successful of these new applications has been for process simplification at cost-conscious DRAM manufacturers. Traditional CMOS technology required two separate mask steps to dope each of the gates in the CMOS pair with n- and p-type species.

   Figure 4. Dual poly gate counter doping process.Click here to enlarge image

   With UHD capability, such as that provided by plasma doping tools, DRAM manufacturers are able to eliminate one poly doping mask step. Instead of doping deposited undoped poly twice, with two masks and two implants, chip fabs can deposit n-type doped poly and with one mask compensate one of the gates in a CMOS pair with p-type dopant inverting n-type poly gate to p-type. This is known as the dual poly gate process (Figure 4).

   In addition to very high dose capability at low energy, plasma-based tools provide conformal doping. Beam-line-based tools place all dopant uniformly into the wafer at a variably prescribed angle. Plasma doping tools dope all surfaces and sidewalls isotropically. This opens up enabling applications for CMOS image sensors where conformal doping of shallow trenches has shown appreciable reduction in dark current.⁸ Future higher-performance low-power 3D transistor schemes may require the conformal doping capability of plasma doping.

   Precision materials modification (PMM)

   Over the past five years, implant transitioned from dirty, high-risk batch processing to ultra-clean single-wafer technology. This cleanliness opened new growth avenues. Chip makers now have no problem adding implant steps because single wafer implanters have been identified as some of the cleanest tools in the fab. Consequently, investigations into whole new realms of applications have begun to open up. Some of the more promising opportunities include etch stop, photo-resist modification and silicon cleaving. All of these opportunities require high levels of precision in incident beam angle, dose rate, dose uniformity, dopant placement accuracy, temperature control, energy control and defect control. Specifically, PMM applications have huge potential to enable actual scaling through modifications to photo-resist or surface materials requiring patterning.

   Conclusion

   Implant is returning to the forefront of device design and is now being seen as an enabler for 32nm and 22nm transistors. The challenges of device leakage, shallow junction creation, device shrinkage, and rapidly escalating costs are pushing the limits of Moore’s Law. By providing innovation in a traditionally productivity-driven technology, implant will help move the industry to the next step and encourage device scaling and performance improvement.

   References

   1. VLSI Research History of CMOS, www.vlsiresearch.com.
   2. B. Colombeau, A. J. Smith, N.E.B Cowern, B.J. Pawlak, F. Cristiano, R. Duffy, et al., “Current Understanding and Modeling of B Diffusion and Activation Anomalies in Preamorphized Ultra-Shallow Junctions,“ Mat. Res. Soc. Symp. Proc. Vol. 810, pp C3.6.1-C3.6.12 2004.
   3. A. Renau, “A Better Approach to Molecular Implantation,“ Proc. of the 7th Intl. Workshop on Junc. Tech., pp 107-111, 2007.
   4. S. Endo, Y. Kawasaki, T. Yamashita, H. Oda, Y. Inoue, “Formation of Low Resistive S/D ???Extension using Carborane Molecular Ion Implantation for Sub-45nm PMOSFET,“ 2008 International Conf. on Solid State Devices and Materials ??? Proceedings are to be published.
   5. T. Yamashita, M. Kitazanwa, Y. Kawasaki, H. Takashino, T. Kuroi, Y. Inoue, M. Inuishi, “Advanced Retrograde Well Technology for 90nm Node Embedded SRAM by High-Energy Parallel Beam“ Japanese Jour. of Appl. Phys., Part 1 41(4B), pp. 2399-403, 2002.
   6. Y. Hai, E.N. Shauly, “Influence of Batch-to-Batch Substrate Variation and Cone Effect on High Energy Implant Distribution Profile,“ 14th International Conf. on Ion Implantation Tech. Proc., pp. 287-290, 2002.
   7. W. J. Lee, T. Thanigaivelan, H. Gossmann, R. Low, B. Colombeau, K. Lacey, M. Merrill, A Renau, “Benefits of Zero Degree Single Wafer High Energy Implants for Advanced Semiconductor Device Fabrication,“ 17th Intl. Conf. on Ion Implant Tech , pp. 261-264, 2008.
   8. C.R. Moon, J.J. Jung, D.W. Kwon, J.R. Yoo, D.H. Lee, K. Kim, “Application of Plasma-Doping (PLAD) Technique to Reduce Dark Current of CMOS Image Sensors,“ IEEE Elect. Dev. Lett., VOL. 28, NO. 2, pp. 114-116, 2007.

   James Kawski received his BSEE from the Rochester Institute of Technology and is manager of market research and communications at Varian Semiconductor Equipment Associates 35 Dory Road, Gloucester, MA 01930 USA; ph.: 978-282-2234; email [email protected].

   Mark Merrill received his BS in electronic engineering from Maharishi International U. and is general manager at Varian Semiconductor Equipment Associates.