Steady progress reported on HK+MG for 32nm and beyond

02/01/2009

Chipmakers are trying many paths toward high–k metal gate dielectric (HK+MG) CMOS for 32nm and beyond. An assortment of papers at IEDM 2008 in San Francisco, CA, showed steadily improving results even though the routes may vary. Using high–k with metal gates not only enables a return to some scaling, but as Intel’s Mistry et al. showed at IEDM 2007, gate leakage also can be reduced 25?? for nMOS and 1000?? for pMOS. But getting to uniform manufacturable devices presents some tough challenges.

Different workfunctions (Wf) are needed for metals in nMOS and pMOS devices, and the HfO₂ compounds most used for the dielectrics tend to diffuse unlike the very stable SiO₂ they are replacing, pointed out Serge Biesemans, director of CMOS technology R&D, IMEC. Further, strain enhancement may be eroded as mobilities shift. Most chipmakers chose a gate–first approach for the metals, using PVD, not realizing at first that subsequent high–temperature process steps would change material properties, Biesemans explained. Intel chose a gate–last approach, which looked more difficult to engineer but easier from a physics point of view, he added. Developers were aware that the barrier layer, capping layers, and interfaces were critical, and they continue to report steady progress in device performance.

Figure 1. Schematic of a hypothetical metal gate consisting of grains with three different orientations, and hence different work function values of φ1, φ2, and φ3 and occurrence probabilities of P1, P2, and P3, respectively. (Source: IEDM)Click here to enlarge image

The Wf, or minimum energy (eV) to remove an electron from a solid surface, depends on a combination of the chemical potential of the bulk material plus a surface dipole potential which is a function of the orientation of metal grains within the gate (Figure 1). This introduces a new source of random variability, pointed out Hamad Dadgour, UC–Santa Barbara, and co–authors from UCSB, AIST (Tsukuba, Japan), and Intel (IEDM 2008 paper 29.6). They developed modeling and analytical techniques for predicting the Wf variation for different metal compounds, helping device designers to predict and minimize V_t variation.

Inserting some lanthanum after the high–k nFET can move the Wf 400–500mV according to Biesemans. An AlO₂ cap can lower V_t in pFETs, but only about 200mV, he said. SiGe channels can lower the V_t 200–300mV, and only one cap is needed instead of two. SiGe also adds strain on silicon, giving about 15% I_dsat improvement, he added.

Figure 2. Increased channel strain due to RMG process flow. (Source: IEDM)Click here to enlarge image

In a late IEDM 2008 paper (27.9), Intel reported on its 2nd–generation HK+MG transistors, with SiGe, using a replacement gate scheme (Fig. 2) that adds about 4% to process cost, according to S. Natarajan, et al. Drive currents were the best reported yet for 32nm (Fig. 3), with 112.5nm contacted gate pitch, the authors said. There was an average 40% improvement over the previous 45nm devices, according to Natarajan. The techniques were used for the largest SRAM yet reported, he added, with more than 1.9B transistors. He concluded that the technology will be production–ready by 2H09.

Figure 3. nMOS (top) and pMOS (bottom) Idsat vs. Ioff at 1.0V. (Source: IEDM)Click here to enlarge image

C.H. Diaz et al. of TSMC reported on a HK+MG gate–first 32nm Hf–based technology for high–performance, low–power applications. The authors reported use of SiGe and stress from contact–etch–stop layers for strain enhancement, avoiding interfacial oxide regrowth while maintaining near band–edge Wf. Dense SRAM cells (0.15μm²) were produced using high–NA 193nm immersion lithography with aggressive resolution enhancement techniques, Diaz reported.

Another gate–first HK+MG approach for 45nm CMOS on SOI was reported by K. Henson of IBM with co–authors from Freescale and AMD. Conventional processing using embedded SiGe and dual–stress liners, the authors said, overcomes limitations to gate length scaling while avoiding the thermal instabilities that lead to V_t shifts and crystal regrowth in the gate stack.

No additional stress enhancers were used to achieve high drive currents. Henson was asked how thermal processing problems were avoided, but he would not provide details.

Another approach to strain enhancement for 45nm HK+MG CMOS devices by using (110) oriented Si substrates was presented by P. Packan et al. of Intel. The authors reported a 15% I_dsat improvement for pMOS devices, with a record 1.2mA/μm drive current at 10V and 100mA/μm I_off. Degradation of nMOS devices can be reduced by 2D confinement and device stress effects, the authors’ analysis showed.

As the industry pushes to 22nm, power will have to be reduced even further, and exotic structures like FinFETs will be considered. Chipmakers would like to get down to 0.5–0.6V_DD with high mobility channels, according to IMEC’s Biesemans. Achieving high mobility may require compound semiconductor devices, combined with high–k dielectrics—and there was a whole session (15.1–15.6) dedicated to this approach at IEDM, he pointed out. Stay tuned. —B.H.