The technomics of 22nm
02/01/2009
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C. Albertalli, Mentor Graphics, Wilsonville, OR USA
What is the most viable path to enabling the design shrink to 22nm? Will a solution emerge that overcomes the technical and economic hurdles currently being anticipated in both manufacturing and design? EUV is still facing substantial technical and economic uncertainties, and multiple challenges must be overcome to enable 22nm production with 193nm wavelength immersion lithography systems. With little help available from scanner optics, the industry faces the high mask cost and scanner throughput penalties of double patterning. Restrictive design rules (RDRs) could help solve the litho problem, but RDRs constrain IP migration and place strict limitations on designers, which will extend design cycles, limit creativity, and ultimately impact design cost and time–to–market.
Extensions to traditional resolution enhancement technology (RET) are not likely to provide sufficient process margin to overcome the low–k1 photolithography challenges of 22nm production. Simulation model accuracy will continue to improve to meet demanding error budgets at 22nm, and correction features, such as adaptive fragmentation, will be available to the optical proximity correction (OPC) engineer for dynamically adjusting mask correction features. However, the physics of 22nm lithography ultimately require new technology to produce sufficient resolution and contrast to achieve an acceptable manufacturing process window. The industry has invested substantial resources to explore new options: inverse mask lithography, double exposure techniques, and polarized illuminators have all been developed and evaluated to assess their potential contribution to the 22nm shrink.
A promising alternative that addresses both technical and economic issues is the ability to concurrently optimize both the illumination source and the mask. Concurrent illuminator–mask optimization adds two additional capabilities to the photolithographic toolkit: pixel–based optimization of the illumination source; and joint optimization of the source shape and mask for individual IC designs.
Early results of concurrent illuminator–mask optimization show promise for reducing dependence on double patterning, and providing substantial improvements in the process window. However, there are substantial challenges to overcome. “Pixelated” scanner illumination sources that allow detailed light intensity patterns to be programmed independently for each IC design must be developed. We also need non–linear increases in computing capacity to enable cost–effective turnaround times without driving datacenter hardware, software, space, power, and cooling costs through the roof.
This brings us to the “technomics” of 22nm. How does the industry address the development of a holistic solution that spans multiple segments of the IC manufacturing supply chain in time for leading–edge 22nm IC development? At a time when the economics of IC manufacturing are under pressure from a global recession, a collaborative effort is the best way to assemble both the technical and economic resources to enable commercialization of the 22nm shrink.
IBM’s Computational Scaling Initiative is a model for such a collaborative development approach, spanning multiple disciplines and suppliers to deliver timely solutions at an optimum cost. By bringing together exceptional expertise in the critical areas of wafer manufacturing, computational lithography, software development, high–performance computing, and algorithmic IP, the initiative demonstrates how concurrent technology development of both process and tools within a manufacturing environment can enable more rapid technology delivery while sharing overall risk.
As the challenges of extending the IC roadmap grow beyond the capabilities of a single entity, this unique collaboration provides a model for aligning efforts to enable timely technical and economic solutions for IC technology development.
Charlie Albertalli is a director of product marketing at Mentor Graphics Corp., Wilsonville, OR, USA; email [email protected].