Strain characterization: techniques and applications

02/01/2009

M. Belyansky, A. Domenicucci, N. Klymko, J. Li , A. Madan, IBM Semiconductor R&D Center, Hopewell Junction, NY USA

The extensive utilization of strain engineering in the semiconductor industry led to the subsequent development and refinement of a variety of analytical techniques that helped to improve manufacturing control of stress level in thin film, as well as to measure strain on individual devices. This paper covers the basics of several strain characterization techniques illustrated by the applications examples.

Strain generation in silicon is one of the major knobs used to boost metal–oxide–semiconductor field effect transistors’ (MOSFET) performance [1]. Silicon can be stressed in various directions, resulting in localized strain fields whose magnitudes are reflected in the values of the silicon piezoresistance coefficients [2]. In simple terms, tensile strain in the silicon channel is beneficial for electron mobility, while compressive stress increases hole mobility.

Biaxial strain can be applied by depositing silicon on a relaxed SiGe substrate, which is beneficial for both electron and hole mobility [3]. A uniaxial compressive or tensile strain in the silicon channel can be generated by introduction of an embedded SiGe or SiC layer, respectively, into the source–drain region of a device. Another powerful way to produce uniaxial strain is to deposit a compressive or tensile liner film around the transistor gate. High–stress silicon nitride liner films strain the underlying silicon transistor channel leading to a substantial increase in device speed. This technique has been successfully incorporated into the dual stress liner (DSL) technology where the performance of both nFET and pFET transistors is enhanced [4].

The advances in strain engineering call for accurate and reliable strain characterization, which becomes increasingly important for simulation, design, and fabrication of strained CMOS devices. The electrical impact of strain on a device is usually measured either on real product or on so called “stress macros” (specially designed test structures). However, electrical data are difficult to compare or interpret without an independent strain metrology reference. Strain metrology work coupled with TCAD type simulations helps to optimize and predict the effects of various stressors on carrier mobility in Si. Strain is defined as ΔL/L; Strain=Y*Stress, where ΔL is the displacement of a silicon lattice and Y is Young’s modulus.

Strain measurement techniques

Several major strain measurement techniques are listed in Table 1. A simple wafer curvature measurement before and after film deposition coupled with thickness data (typically obtained by optical ellipsometry) gives an accurate estimate of film intrinsic stress (Stoney equation [5]), which later could be correlated to device data. However, the curvature measurement is mostly applicable to blanket (non–patterned) films and gives no insight into real device strain, geometrical effects, or strain gradients.

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Raman spectroscopy and X–ray diffraction (XRD) based techniques are limited by spatial resolution, but have good sensitivity to Si strain and can measure strain gradients. An added advantage is the ability of X–ray, UV, and visible photons to penetrate dielectric film layers (e.g., nitrides and oxides) for in situ analysis of the underlying active area region. Transmission electron microscopy (TEM) based techniques such as nano–beam diffraction (NBD) and convergent beam electron diffraction (CBED) can measure strain on an individual device, however they can not be routinely used for in–line metrology. This is due to the destructive nature of TEM analysis, in addition to the substantial amount of time needed for sample preparation and data analysis.

In practice, a combination of all the techniques listed in Table 1 are used and correlated with device electrical shifts attributed to strain engineering. Once such correlation is established on a variety of test structures, strain metrology techniques have been shown to predict the performance of state–of–the–art strained CMOS transistors successfully.

Raman strain metrology

The Raman effect is the inelastic scattering of photons from the vibration–induced phonon modes in a material. Raman scattering is a two–photon process whose probability is dependent on the polarizability change in the bond during its phonon motion. A monochromatic (laser) source is used, and the resulting spectrum records the scattering intensity relative to the shift in frequency of the laser:

hω_laser - hω_scattered = hω_phonon

In crystalline materials such as silicon and SiGe, the presence of strain causes a shift of phonon peak positions. The magnitude of the shift, compared to an unstressed reference, determines the amount of strain. The direction of the shift determines the sign of the strain (compressive or tensile). These strain shifts have been precisely calibrated using high resolution XRD, so the determination of strain using Raman spectroscopy can be accomplished with ~0.005% sensitivity using high–resolution spectrographs with sensitive CCD detectors.

Instrument configuration couples an optical microscope to a high–resolution spectrograph, with confocal 180° backscattering collection optics. Lateral spatial resolution depends on the laser wavelength and the numerical aperture of the objective, and can be as small as ~400nm for UV wavelengths. or pushed even smaller with the use of solid immersion lenses [6, 7]. Sampling depth also depends on laser wavelength as well as the absorption characteristics of the material under study, and with UV wavelengths below 350nm, the sampling depth in Si and SiGe is ~10nm, making this technique suitable for thin–layer analysis [8].

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Figure 1a shows results of a pFET device test structure fabricated with embedded SiGe in the source/drain regions to compressively stress the channel region. Intrinsic Si0.85Ge0.15 was selectively grown in the recessed S/D regions with ~80nm thick eSiGe. The Raman spectrum shown in Fig. 1b was collected using 325nm excitation from a HeCd laser, and 100?? 0.9N.A. UV objective, to provide both spatial and depth resolution required to probe the epitaxial SiGe region between the gates. The dominant feature in the spectrum is the Si–Si phonon at ~515cm–1, and this peak position is used to determine the percent of strain [9].

There is good agreement between the strain result from the Raman test structure and the result measured by CBED in the channel region. The attractive feature of Raman spectroscopy is a relatively good lateral resolution (upwards of 200nm with the use of UV lasers). While the length of an individual transistor’s Si channel is much smaller, there are typically some macros and areas on the chip that have sub–micron dimensions with a film stack identical to a real device. Raman analysis of such structures can shed some light on the strain value on a real device, which is impossible to achieve with XRD or wafer curvature measurements.

Additionally, there is some ability for depth profiling either by varying the excitation wavelength or by using physical unlayering techniques combined with UV excitation for near–surface sampling depth. Future improvements in Raman microanalysis of localized strain include coupling of AFM tips to the Raman microscope for near–surface measurements with spatial resolutions in the 100nm range [10].

In another application, UV Raman measurements were made on shallow trench isolation (STI) test structures to characterize localized strain in active area regions between and beneath the STIs (since the laser probes through the STI material). Line scans across features with various sizes of active area line and trench spacing showed changes in strain at the edge of the STI fill, thereby differentiating the strain response for different types of STI fill material. Various oxides including high density plasma, ozone/TEOS, and spin on glass, as well as compressive and tensile nitride liner materials, have been characterized in this way with UV Raman spectroscopy.

XRD strain metrology

XRD is the only non–destructive technique that can directly measure the strain in the crystalline lattice of epitaxial films. X–ray methods do not require calibration standards, and have been successfully used to measure composition and residual strain in epitaxial layers of SiGe, SiC, and other stressors. Specialized incident optics are needed to measure small changes in the lattice spacing due to compression or tension. The incident X–ray beam must be highly monochromatic with a well–defined wavelength and small angular divergence. While early measurements of strain have been done on blanket wafers in a lab environment, recent advances in incident optics and generators make it possible to measure strain in patterned features as small as 70??m. Positional accuracy of the goniometer is important, but not a problem as the rocking measurements are relative measurements demanding accuracy over a small range (<2°).

In addition, automation of XRD equipment has enabled the use of this technique for routine in–fab measurement [11]. In–line X–ray techniques are routinely used to monitor strain in epitaxial films. With an in–line XRD tool, the same wafer and spot can be measured at different process steps to determine variation in strain with implants and anneals. This enables process integration schemes that help to retain a high level of strain.

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Typical XRD scans from an eSiGe layer deposited on Si are shown in Fig. 2. Experimental data (black) is simulated (red) using commercially available software to determine the strain (related to the position of the SiGe peak) in a SiGe film. The strain is then converted to the Ge concentration using Dismukes Law [12]. The fringe spacing is related to film thickness, so both thickness and strain information can be obtained from a single scan. An example of typical precision achievable with in–line XRD analysis in case of a SiGe epitaxial stressor sample is: thickness of 500Å @ 1% (1σ); Ge concentration of 19.95% @0.5% (1σ).

Figure 3a shows the effect of commonly used semiconductor processing steps on SiGe strain, measured on 100??m–sized test sites using micro XRD. An increase in the strain with boron implant can be explained by swelling of the lattice due to boron at interstitial sites. Subsequent processing steps (source/drain implants and high–temperature anneals) decrease the strain. The strain decrease after all implants and high–temperature anneals could be partially explained by boron incorporation into substitutional Si sites, however, it is hard to determine the exact cause from the XRD data alone.

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Figure 3b presents the corresponding 442nm Raman spectra for the as–deposited (post epi) film, and the film after all implants and anneals. The Raman data for the as–deposited film is consistent with a fully strained epitaxial film, in good agreement with the XRD result. However, after all implants and anneals, the Raman spectrum shows significant defectivity in the film, as evidenced by the broadening and reduced intensity of the Si–Si phonon peak in the SiGe layer. TEM analysis of the same sample showed stacking faults and numerous V–defects in the top layer of this film contributing to the strain loss. The XRD, Raman, and TEM give complementary data in which the XRD result for strain is not confounded by the presence of defectivity, while the Raman sensitivity to defectivity is corroborated by the TEM.

Channel strain measurements by CBED and NBD

Despite the recent progress in Raman– and XRD–based techniques, the inherent spatial resolution limitation prevents these techniques from measuring strain directly on state–of–the–art (sub–50nm) MOSFET channels. Techniques with high spatial resolution, such as CBED and NBD, have been successfully used to characterize strain/stress in individual transistor channel regions [13–17]. This data is critical to correlate channel strain to device performance and to optimize integration process schemes.

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CBED and NBD are both electron diffraction techniques (Fig. 4). NBD uses a nearly parallel electron beam 15–25nm in diameter, which gives a traditional electron diffraction pattern. Strain can be determined from the separations of the diffraction spots that shift with strain and are inversely proportional to its magnitude. CBED, on the other hand, uses a focused nanometer sized probe that gives rise to diffraction patterns with disks. For certain crystallographic directions, the central disk of a CBED pattern contains well–defined high–order Laue zone (HOLZ) lines that shift with strain. Strain can be determined from line shifts by fitting simulated CBED patterns to experimental ones using least squares fitting routines. In both techniques, it is essential to have an unstrained area within the field of view to collect reference (zero strain) patterns so that experimental errors can be minimized.

The CBED technique is inherently more sensitive for strain determination (0.05%) when compared to NBD (0.1%), because CBED is based on higher order diffraction reflections, which are more sensitive to changes in interplaner spacings. However, CBED suffers from the requirement to tilt samples for well–defined HOLZ patterns. In practice, it is useful to have both techniques available to see which one suits a given device geometry better.

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To show the usefulness and comparison of TEM–based techniques, CBED measurements were made on pFET structures after depositing 80nm of embedded Si0.85Ge0.15 stressors in the S/D regions. Similar but larger structures have been analyzed by Raman and XRD. CBED analysis was performed in a JEOL 2010F TEM equipped with a Gatan energy–filter, in the scanning transmission (STEM) mode with a probe size of 1nm. CBED patterns were recorded from 25nm to 1000nm below the gate at various intervals. The patterns were then analyzed using the ASAC software developed by SIS [13, 15] using the CBED pattern at 1000nm below the gate as an unstrained Si reference. The lower curve in Figure 5 gives the resulting E_xx component of the strain tensor as a function of depth for the 80nm eSiGe case. The plot shows that the strain reaches a maximum value of –0.5% (E_xx component) in the channel region, and decreases to essentially zero at 150nm below the surface.

NBD measurements were made in the center of the channel regions of the identical gates on which the CBED analysis above was performed. The JEOL 2010F TEM was used again, this time in the NBD mode of operation with a probe size of 20nm. The average strain measured by NBD in the E_xx direction is –0.55%, which is in good agreement with the CBED measurement of –0.50% and with TCAD simulation.

TEM–based channel strain measurements can provide insight into the effect of processing steps on channel stress, and proved very instructive in optimizing device performance. Channel strain for eSiGe devices can be affected by several process conditions, such as thickness of eSiGe, proximity, and source/drain implantation and anneal. All of them can lead to eSiGe relaxation as shown by XRD and Raman. CBED measurements confirmed these findings by determining strain values in the Si channels in pFET devices fabricated with different process conditions (top 2 curves in Fig. 5). The CBED results show that channel strain is reduced from –0.5% to –0.2% when the eSiGe depth is reduced from 80nm to 40nm. The channel strain is further reduced to –0.1% by a boron implantation process that resulted in the formation of misfit dislocations at the eSiGe/Si interface, relaxing the eSiGe [16].

Conclusion

Raman, XRD, and TEM strain measurement techniques aided by blanket wafer bow stress measurements form a reliable basis of Si strain metrology and are currently used in the semiconductor industry for CMOS strain engineering optimization and characterization. These techniques have proven to correlate well with transistor device performance and are providing insights on the mechanism of a variety of stressors and stress–inducing techniques such as eSiGe, eSiC, STI stress, stress memorization, and stress proximity techniques.

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For more information, contact Michael Belyansky at IBM Microelectronics, 2070 Rt. 52, Hopewell Junction, NY 12533 USA; phone: (845) 892–9265, email: [email protected].