Addressing 32nm half-pitch challenges with double-patterning lithography
12/01/2006
Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. Conventional immersion lithography, however, is unlikely to take the industry to 32nm half-pitch. Various double patterning lithography (DPL) techniques have been proposed to address this limitation. This article discusses promising interim solutions for DPL control.
Across the globe, the semiconductor industry is developing at least three advanced lithography strategies in parallel: hyper-NA immersion lithography, double-patterning lithography, and EUV lithography. The most advanced immersion lithography tools are intended for 45nm half-pitch features and are limited to 1.3-1.35 NA by the refractive index of the water used as the immersion fluid. Higher index fluids are being developed, but progress in developing the high-index glasses needed for immersion lens technology is slow. EUV has myriad development issues that are likely to induce delays, including source power, optics lifetime, resist sensitivity, and mask defectivity. As a result, advanced semiconductor companies with density-sensitive product lines (e.g., flash memory) are likely to drive the development of double-patterning lithography (DPL) as a key means of reducing effective pitch.
Double patterning usually consists of a first exposure step, followed by a hard-mask etch. A second exposure with a different reticle is followed by another hard-mask etch. At this point, critical dimension (CD) and overlay error combine in the resulting pattern so that
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The CD error (CDE) is the sum of edge placement errors in the first and second patterning steps, including intra-layer misregistration (i.e., overlay error, OLE). In dense patterns, OLE can produce lines that are alternately too large and too small; this is the first major objection to DPL.
The second major objection to DPL is cycle time, which increases due to the extra photo and etch steps. The revenue loss (ΔR) arising from increased cycle time (Δt) is expressed in the modified Leachman model shown below:
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Here, D is the rate of good dice out, and P is the average selling price at time (t) over the interval (T). If P were constant, revenue loss would be zero; but, for products like flash memory, price can decline 50% in a year, resulting in extreme sensitivity to cycle-time variation. As a consequence, attempts may be made to shorten the cycle, perhaps by eliminating a hard mask step (Fig. 1). Since etching is required, increasing scanner throughput is only a partial solution to the cycle-time problem. Immersion scanners at 130wph (125 shots per wafer @ 30mJ/cm2 per shot) are already approaching maximum practical speeds.
Enabling overlay control for DPL
DPL is up to three times more sensitive to OLE due to the interaction of overlay with CD. Consequently, overlay metrology must represent in-die misregistration accurately to enable the higher-order corrections required for DPL. To improve accuracy, overlay will be measured in the die using small grating-based targets (Fig. 2) embedded in dummy-fill structures (logic) or in DFM-optimized areas (memory). Since current sampling is typically limited to the corners of the lithographic field, the new approach results in more representative sampling, reduction in model residuals, and improved overlay correction. The yield benefits of in-die overlay metrology are already evident in the current generation of semiconductor technology, and these benefits are expected to increase monotonically as the industry approaches the 32nm node.
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State-of-the-art immersion lithography tools have dual stages, allowing dry metrology and wet exposure to be performed in parallel. Within the wafer, exposure uses alternating scan directions. These operations can produce wafer-to-wafer and field-to-field overlay error, respectively (i.e., dual stages can create wafer-to-wafer overlay error, and alternating scan directions can create field-to-field overlay error, respectively). In addition, immersion typically requires a water dispensing system with an air curtain for droplet containment. Rapid motion of the wafer under the lens may create inhomogeneous thermal conditions, resulting in unmodeled OLE. Notwithstanding, overlay specifications for the most advanced 45nm lithographic technology are about 6nm (Fig. 3) for a single tool (~26×33mm field). Tool-to-tool variation reduces this specification to 8-10nm. DPL, however, requires a specification closer to 3nm. As a result, tool dedication, stage dedication, and significant control innovation may be needed to support future DPL strategies.
Enabling CD control for DPL
DPL is much more sensitive to resist profile error when cycle time is forced down by performing the final etch directly after the second photo step. Part of the pattern is defined by a hard mask and part by resist. Consequently, resist profile control will be critical in order to match the result of the first patterning step. To improve resist profile control, three-dimensional focus-exposure windows can be created using data from 3D scatterometry, which provides a deluge of multivariate wafer-state information that can enable process adjustment. For example, initially, measurements of bar structures in grating patterns will extract width, length, and end-wall angle data that correlate strongly with focus and exposure dose. Later, as with overlay metrology, such interim methods may be supplanted by true in-die profile and shape metrology.
Some companies have developed and patented alternative pitch splitting methods based on sidewall spacer formation and etching. In the simplest of cases, sidewall spacers are formed on each side of a sacrificial structure that is then etched away selectively. The spacers become hard masks for subsequent etching of the underlying substrate. In this way, two structures are formed where one existed before. With respect to overlay, the structures are inherently self-aligned if the CD error of the sacrificial structure is zero. If the CD error is not zero, CD and OLE are once again confounded; but, for many designs, CD control may be an easier problem. In fact, scatterometry has been shown to be an effective control methodology for these structures. Given the benefit of excellent CD control, nonlithographic solutions to pitch reduction may prove the most cost effective, particularly for memory products.
Conclusion
Practical interim solutions, including in-die overlay metrology and 3D scatterometry, exist to support control of double-patterning lithography for the 32nm node and beyond. These solutions can provide accurate process metrics for DFM and APC strategies. Moreover, if they can be leveraged for yield improvement and cycle-time reduction, standard factory models indicate compelling economic benefit. In addition to cycle-time issues, interaction of CDE and OLE will be a critical problem at 32nm half-pitch. Measurement, analysis, and control capabilities must improve dramatically to address these future needs.
Kevin M. Monahan is VP of technology in the Parametric Solutions Group at KLA-Tencor Corp., MS-3-2040, One Technology Drive, Milpitas, CA 95035; ph 408/823-1549, e-mail [email protected].