Issue



Improving yield in advanced technologies by modeling variability


12/01/2006







At the 45nm technology node and beyond, accurate modeling of parametric variations arising from lithographic, stress, and doping sources is crucial for achieving a more realistic assessment of circuit performance, such as timing closure at the design stage. Technology computer aided design (TCAD) that accurately predicts manufacturing process and device characteristics is indispensable for modeling physical phenomena in manufacturing processes, such as those found in strained silicon engineering, and their effects on device parametrics. Systematic TCAD-based methodologies simulate the complexity of variability and generate models to incorporate it into the standard compact models, enabling designers to perform realistic circuit analyses for actual manufacturing technology.

As MOSFET device dimensions approach their fundamental limits [1-3], parametric variation in manufacturing has become a critical limiting factor for device performance and design yield of advanced CMOS technologies [4-7]. The sources of variation extend beyond traditional intra-die (across-the-chip) and inter-die (chip-to-chip) variation into complex lithographic, thermal, doping, and stress sources.

While lithographic variability and optical proximity effects have received considerable attention, other sources of variation are equally critical for advanced technologies. Well proximity [8] and halo shadowing [2] effects contribute to localized doping variations, whereas stress from shallow trench isolation (STI) regions can unintentionally affect the stress in the channel of nearby devices. These effects interact with intentional stress sources used in advanced technologies to improve device performance, such as nitride liner films in nMOSFETs and silicon germanium (SiGe) source-drain regions in pMOSFETs [9], resulting in changes to the MOSFETs’ electrical performance. The complexity of these effects and their interactions has rendered traditional corner modeling approaches inadequate at 45nm and below. As a result, new design methodologies that can both mitigate and quantify the impact of variability on design performance and yield are beginning to emerge. These design methodologies inevitably require compact models [5-6] to account for these effects.

Recently, there has been tremendous interest in applying the parametric variation modeling approaches (based on device characterization data) from manufacturing technologies into circuit simulation [4-8]. This approach is not only expensive since it requires processed wafers, but also time consuming because it is limited by the inability of metrology tools to measure the source of the variation in the device under test (DUT). On the other hand, a TCAD-based methodology can directly correlate process variability to device performance, thus providing an efficient and cost-effective way to generate process-aware SPICE models.

Manufacturing variability

Systematic, or intra-die, variability is the variation of electrical parameters of identical devices and interconnects from location to location in a given die. For CAD, these identical devices are electrically described by the same layout parameters, such as length, width, and height, and a single set of parameters is used to accurately describe the electrical characteristics of all transistors or all interconnects. For scaled transistors and new manufacturing steps, such as chemical mechanical polishing (CMP) and copper damascene, this assumption is no longer valid. Identical devices from the same layout show different device characteristics due to printed line width at the end of the gate, well proximity effect-inducing mechanical stress in the channel, and so on. Similarly, the resistance and capacitance of metal lines vary over the die depending on the pitch and spacing of the metal lines, as well as on the pattern density around the metal lines due to lithography, etching, deposition, and CMP effects.


Figure 1. Flowchart showing TCAD-based parametric variability modeling for circuit simulation. Here, {Pi} and {Gi} represent the sets of front-end and back-end process parameters, respectively.
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Inter-die, or random, variability is the variation of the electrical parameters of a device or interconnect at the same location on different die. Random variability arises from variations in process parameters such as lithography, ion-implant dose, and film thickness across the wafer and from wafer to wafer. These, in turn, are related to the spatial uniformity of individual process steps inherent to the equipment and the statistical distribution of process parameters for a given equipment setting. Typically, these variations are included in the corner case models.

The total parametric variability is the sum of the systematic and random variability. For more advanced technologies, the systematic variability is the same magnitude or larger than the random variability, causing the net variability to increase from one technology node to the next. To design a robust circuit, a chip designer needs models that accurately account for both random variability resulting from process variations and systematic variability related to layout.

Process-induced parametric variability

Successful design for manufacturing (DFM) entails feeding manufacturing information back into design. By combining calibrated TCAD models [10-12] with a global SPICE model extraction strategy, self-consistent process-dependent compact models that include process-parameter variations as explicit variables can be generated. A calibrated TCAD flow ensures the accuracy of simulation against silicon, whereas the extraction brings a set of process parameters {Pi}, such as implant dose, anneal temperature, gate critical dimension (CD), and gate oxidation temperature, into the SPICE model.


Figure 2. Variation of ring-oscillator frequency as a function of percentage variation for the four different process parameters depicted.
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This method is analogous to traditional principal component analysis (PCA) [13], in which the process variables serve as principal components. The advantage of this methodology is that one can perform statistical analysis and also study the effect across a die of changes in a specific process parameter, such as the gate-oxide thickness variation. Such an analysis allows designers to assess the effect of on-chip variations on the timing characteristics of digital circuits. This approach works in both directions: measurable process variations in the manufacturing line into design and the design sensitivity on process to manufacturing.

Process and device simulations. The TCAD-based SPICE model extraction flow, shown in Fig. 1, can be used to model parametric variations. For an accurate numerical simulation, the process and device models are calibrated to silicon data. For digital circuits, the timing delay of library cells depends on the specific set of device and interconnect process parameters used. The static timing analyzer (STA), in turn, uses the timing and resistance-capacitance (RC) models to determine timing for paths with different combinations of device and interconnect process conditions. Proximity effects are added as needed for timing optimization.

The process simulation accounts for all critical physical effects due to pre-amorphizing implant damage, non-equilibrium dopant activation, transient-enhanced diffusion, halo implant, retrograde channel profile, and so on [14]. The device simulation is based on a calibrated transport model and includes the polysilicon-gate depletion effect and the quantum-mechanical effect [14]. The robustness of the simulation structures and the mesh are verified to eliminate any mesh-related artifact [15].

Compact model extraction. In order to extract a compact model, the simulated I-V characteristics are generated for different combinations of key process parameters such as DL (deviation of gate critical dimension from the nominal value), annealing temperature, halo implantation dose, gate oxidation temperature, and threshold voltage (Vt)-adjust implantation dose. I-V data generated from random sample points, along with the corresponding process conditions, is provided to the extraction engine to derive compact SPICE models.

Each BSIM4 SPICE model parameter [16] can be represented as a quadratic function of process parameters. This model is easily scalable to higher polynomial orders for improved accuracy of extraction, which involves extraction of nominal SPICE parameters followed by extraction of the process co-efficient, and then re-optimization of the nominal values of SPICE parameters. Sensitivity analysis is used during extraction to select the process parameters having the highest impact on the device characteristics. Also, the use of a penalty function [17] forces extraction of physical values of SPICE model parameters. This process-aware SPICE model allows designers to analyze circuit sensitivity due to process variations.

Figure 2 shows the deviation of the ring oscillator frequency with variations in halo implant dose, gate oxidation temperature, the change in gate length (DL), and Vt-adjust implant dose. The frequency of the ring oscillator under nominal process conditions is found to be 66MHz. Gate oxidation temperature, n-halo implant dose, DL and p-halo implant dosage were observed to have significant impact on the frequency of the ring oscillator, in that order.

Layout-dependent variability

The mechanical stress in the transistor channel arising from STI is the primary source of layout-dependent device performance variability, mainly due to the variations in the carrier mobility and threshold voltage [17-20]. The effect of STI is modeled by a length of diffusion (LOD) that modifies the SPICE parameters of isolated transistors depending on layout conditions such as the length of the diffusion rectangle and the gate distance from the adjoining diffusion edge on either side [20]. However, LOD cannot model neighborhood effects such as adjoining diffusions or complicated diffusion patterns involving both convex and concave diffusion corners.

On the other hand, a TCAD-based approach can easily calculate the stress as a function of space between diffusions to accurately model the effect of stress on the electrical performance. The, 3D stress fields from a layout and the stress components along the channel, SL, and perpendicular to the channel, ST, can also be calculated. These components strongly depend on the overall shape of the diffusion island. From the calculated values of SL and ST, the change in the carrier mobility at any point in the channel is determined using the piezoresistive coefficients for bulk silicon [18].

Figure 3 shows the calculated stress fields arising from the STI structure of three diffusion patterns: an H-shaped pattern, a rectangular pattern with a length equal to the central short section of the H pattern, and a long rectangular pattern with a length equal to the longer central section of the H pattern. The stress patterns are very different and indicate that the presence of convex corners in the H pattern causes the pattern to be modified from a rectangular layout, which has only concave corners. The extra corners produce an additional tensile component in SL in the horizontal section. For electrons, the mobility degradation is ~15% for the small rectangular structure and ~7% for the H-shaped structure. For holes, the piezoresistive coefficients are such that the degradation is worse: ~17% for the H-shaped diffusion layout.


Figure 3. Distribution of stress-field components for different diffusion patterns: a) SL and b) ST.
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Typically, the stress from a specific diffusion edge extends for a certain critical distance from the edge, d c. Therefore, the device characteristics are affected by all diffusion patterns within a radius of dc from the transistor channel. Using TCAD, a set of 2D analytical functions can be determined that can estimate the stress field for any 2D layout at any point in the diffusion areas [16]. These can be considered the compact models for the stress. The relationship between the mobility and threshold voltage shift and the stress field is determined from test structures having a simple rectangular diffusion area at the location of the transistor in the actual layout. The compact stress models are linked to a polygon processing system to create a TCAD extraction tool, Seismos [14], which can analyze the change in characteristics for all the transistors in a large block or even a complete design. This tool then modifies the relevant SPICE parameters for the respective transistor in the netlist based on the magnitude of calculated stress.


Figure 4. Change in mobility as a function of the distance between two adjoining diffusions calculated by the Seismos tool for analyzing stress proximity effects in IC designs.
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Again, in advanced CMOS technology, stress is applied using embedded SiGe in the source/drain for pMOSFETs, or dual-stressed nitride liners [9] for nMOSFETs. The magnitude of different stress components is a function of the overall 3D geometry, and hence the transistor properties can vary with layout according to the gate pitch [9] and position of the edge of the nitride cap relative to the diffusion edge. The stress models from each type of source can be modeled and incorporated into Seismos to analyze the variability of transistor performance for multiple stress sources. Figure 4 shows results obtained from this emerging tool.

Conclusion

The parametric variations associated with advanced manufacturing technologies severely impact device performance and yield. Several new methodologies can be used to capture the impact of these variations through novel modeling concepts. A TCAD-based approach can be used to perform efficient process and device analysis leading to accurate compact models that are representative of actual manufacturing technology. Using TCAD and metrology data, parametric variations can thus be modeled to provide designers with an optimized design-synthesis environment.

References

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Samar Saha received his MS degree in engineering management from Stanford U. and his MS and PhD degrees in solid-state physics from Gauhati U., India. He is a senior manager at Synopsys Inc., 700 E. Middlefield Road, Mountain View, CA 94043; ph 650/584-2894; e-mail [email protected].

Xi-Wei Lin received his PhD in physics from the U. of Paris, Orsay, and is director, TCAD DFM solutions, at Synopsys Inc.

Victor Moroz received his PhD in semiconductor physics at the U. of Nizhny Novgorod, and is principal engineer, TCAD DFM solutions, at Synopsys Inc.

Ricardo Borges received his MS in electrical engineering from Tufts U. and is a technical marketing manager at Synopsys Inc.

Terry Ma received his BS in chemical engineering from the U. of California, Berkeley, and his MBAe from the Kellogg School of Management, Northwestern U. Terry is currently group director of marketing at Synopsys Inc.

Dipankar Pramanik received his PhD in physics from Cornell U., and is group director, TCAD DFM solutions, at Synopsys Inc.