New materials take a “BiTe” out of high-end CPU hot spots
11/01/2006
Hot-spots resulting from nonuniform power dissipation over a chip are the bane of manufacturers of high-performance ICs such as CPUs, graphics chips, and DSPs—and as CMOS devices continue to scale and total power dissipation increases, these hot-spots will only become more pronounced. Nextreme Thermal Solutions is readying its nanoengineered films for embedded thermoelectric coolers to help the industry meet the challenges associated with the International Roadmap for Semiconductors (ITRS), which projects high-end CPUs dissipating 200W five years from now.
“Multi-core processors exacerbate the hot-spot issue,” making thermal management more challenging and requiring cooling solutions closer to the die, according to Bob Conner, VP of marketing and business development at Nextreme Thermal Solutions, a 2004 spin-off of RTI International that manufactures nanoengineered films for embedded thermoelectric coolers (eTECs). Cooling close to the die is necessary to handle nonuniform power dissipation, he told SST, because there is significant spreading resistance within the IC package itself. Cooling close to the source of the heat keeps that problem to a minimum.
Nonuniform power dissipation is the result of a small percentage of the die area dissipating a large percentage of power, Conner explained. “As CMOS scales, IC manufacturers will make the performance-critical cores [e.g., fixed-point, floating point units] smaller and faster so they will dissipate more power in a very concentrated area, and these cores are surrounded by a lot of memory that dissipate little power but consume a large amount of die area,” he said. “So as CMOS is scaling, these cache sizes will grow, causing a growth in nonuniform power dissipation.”
 Figure 1. Nonuniform hot-spot cooling. |
TECs, whether bulk or embedded nanoengineered films, are based on the Peltier effect: when current is applied to two dissimilar materials (e.g., p- and n-type), heat is absorbed at one junction and released at the other junction [1]. Typically, CMOS device manufacturers want to keep junction temperatures below 100°C. Nextreme is targeting the hottest hot-spots—those that are typically 5-10°C above the average die temperature (see figure 1).
Strategically placing an eTEC between the backside of the die and the heat spreader creates a temperature inversion at the site of the hot spot. “Essentially, we are moving heat from a low thermal conductivity material, the Si die and the thermal interface material [“TIM1” in figure 1, between the die and heat spreader] to high thermal conductivity materials—the spreader and heat sink,” explained Conner. “So we’re cooling the hot spot by 5-10°C, which impacts reliability, performance, yield, and leakage power.” Conner maintains that this small amount of cooling of the hottest hot spots enables CPUs to bin out at slightly higher chip speeds, thus earning more money for the IC manufacturer.
The eTECs are thin (i.e., 5-10µm thick) nanoengineered films, typically from bismuth telluride (Bi2Te3) and antimony telluride (both p-type and n-type materials), using a modified MOCVD reactor and proprietary processes. After processing, these films have the property of retaining their electrical conductivity while incurring a decrease in their thermal conductivity, vs. the more typical situation where a good electrical conductor is a good thermal conductor. “What you want for a TEC is a very good electrical conductor, so you can move a lot of electrons and holes from the heat absorbing side to the heat releasing side, but a very poor thermal conductor to prevent the hot side from heating up the cold side,” explained Conner.
Because the nanoengineered film is so thin and only millimeters on a side, it can be embedded very close to the die—something that cannot be done with bulk TECs, which are generally 1-in. on a side and 1/4-1/2 in. thick, Conner points out. Because the heat pumping flux (Watts/cm2) of a TEC element is inversely proportional to its thickness, the thin eTEC also has 100x more cooling power than bulk TECs. “This is very important for hot spots because you have very high heat fluxes in a very small area,” he notes.
 Figure 2. Nonuniform heat removal requires a cooling solution close to the die. |
Another advantage for eTECs being so thin is that they can be embedded in the package, to dissipate the excess heat that is due to the package alone (see figure 2). This excess heat is generated by the temperature rise created by the difference in spreading resistance due to the poor thermal conductivity at the Si die and the thermal interface material.
As a point of contrast, Conner notes that bulk TECs are grown in ingots—p-type and n-type—that are sliced and diced into small pellets (typically 1mm thick and 1mm on the side) and assembled between two large ceramic plates. “But these are bulky and relatively inefficient,” said Conner. “You would need to put in 4-5W of power for every 1W of power that is cooled,” he said, noting that the bulk TECs are used in small niche applications such as cooling laser diodes in telecommunications. “What we are doing is replacing those pellets with a thin film.”
Conner added that the eTEC approach complements uniform cooling techniques that apply to the entire chip, such as liquid cooling, refrigeration, and improving existing thermal components (e.g., heat sinks, fans, heat pipes, and heat spreaders). Specifically, eTECs enable designers to avoid over-engineering chip scale thermal solutions by targeting the hot spots. He further maintains that alternative hot-spot cooling approaches such as thermal plugs and bulk TECs in combination with thermal plugs are either too costly, or have CTE mismatch issues. Additionally, jet spray impingement is only in the research stage.
Initially, Nextreme plans to target low-volume/high-value products such as electronics used in oil wells, military applications, and communications infrastructure—basically, high ambient temperature environments. The company is not yet in production but is sampling some early products. “Next year, we’re going to have samples to start product qualification,” said Conner. “There’s an extensive customer qualification process so we’re probably 2-3 years away from starting a production ramp for niche applications, and 3-5 years to move into volume PC applications.” —D.V.
[1] G. Snyder, M. Soto, R. Alley, D. Koester, B. Conner, “Hot Spot Cooling using Embedded Thermoelectric Coolers,” 22nd IEEE SEMI-THERM Symposium, 2006.