Wafer-level packaging boosts yields of chip-on-board image sensors
11/01/2006
Chip-on-board (COB) is the most dominant assembly process used to build over a million camera modules each day of the year. These camera modules are used in camera phones, optical mice, and many other optical devices. However, as the market moves to cameras with ever-higher pixel counts, COB assembly becomes increasingly difficult due to contamination of the optical sensor. An effective way to prevent contamination is to place a cover over the image sensor at the wafer level, and leaving the bond pads exposed allows for full compatibility with the COB assembly process.
Solid-state optical sensors are finding application in an ever-widening variety of products. The largest markets by volume are camera modules for mobile phones, optical mice, and digital cameras. Solid-state optical sensors are also used in large quantities in web cams, document copiers, bar code readers, and positional control systems.
The majority of solid-state image sensors are based on complementary metal-oxide semiconductor (CMOS) technology because it provides a more integrated solution than competing approaches such as charged-coupled device (CCD) technology. A CMOS image sensor comprises a 2D array of photo detectors that provide the electro-optic conversion function, together with some additional electronics for picture and power management. Each light-sensitive area on a chip with its associated electronics is referred to as a picture element, or “pixel.”
 Figure 1. Micro lenses are used to focus the incident light on each pixel onto the light-sensitive area, thereby increasing the low light sensitivity of the image sensor. |
The electronics necessary to provide functionality to the pixel take up real estate on the chip. Thus, light-sensitive areas must be decreased in proportion, which degrades function in conditions where the light intensity is low. To compensate for the light loss, a micro lens is placed on each pixel. Micro lenses are pseudo-hemispherical in shape and serve to focus all of the light that impinges on each pixel onto the light-sensitive area (Fig. 1).
Micro lenses add significant constraints to the further processing and packaging of the image sensors. An air space must exist directly above the lenses for proper function because any material in direct contact will alter the optical performance of the lens. Micro lenses are generally composed of soft, polymeric materials, so foreign particles can easily damage them or become lodged on the surface of the lenses.
The micro-lens manufacturing process often contains a melting step to produce the curved features, resulting in structures with limited temperature stability and restricted range and duration of subsequent thermal excursions. The optical benefits outweigh the other limitations, however, and all quality CMOS image sensors use micro lenses.
Solid-state camera modules
At a minimum, a solid-state camera module consists of a lens assembly and an image sensor attached to a laminate substrate. Figure 2 shows the cross-section of a typical COB solid-state camera module.
 Figure 2. Schematic of typical camera module using COB technology for mounting the image sensor on the PCB (or flexible circuit). |
In principle, COB is readily implemented and cheap. The image sensor is simply mounted on the printed circuit board (PCB) and then wire bonds are used to connect the sensor to the board circuitry. In all stages of assembly, however, the image sensor surface remains exposed to the environment, and particle contamination is a major issue. It is therefore not surprising that more than 90% of defects in COB camera modules are related to contamination by particles.
Exposed micro lenses are at risk of particle contamination until the module assembly is completed. The combination of the delicate nature of the micro lenses and their chemical composition effectively precludes standard semiconductor cleaning approaches. As pixel sizes decrease to permit smaller die and pixel counts increase (i.e. resolution) in response to market demand, this problem will get worse as the critical particle size to create a reject gets smaller. Compounding the issue is that notoriously dirty processes, such as dicing, die thinning, and probe testing, are all part of the COB-based assembly flow.
The short-term solution to keep particles away from ever-smaller pixels is to invest in cleanrooms and operator training. However, many solid-state camera module manufacturers are already operating Class 10 environments or better, so there is not a great deal of scope for further improvement at affordable cost. The net effect is a tendency toward increased yield loss with increasing sensor resolution and decreasing pixel size.
Wafer-level technology
Conventional semiconductor die are fabricated in parallel at the wafer level, then diced and singularly housed in discrete packages so that the costs of assembly are incremental for each die. Wafer-level packaging (WLP) is an alternative approach in which the die are packaged while still in wafer form, and the wafer is then singulated to individually packaged die. WLP has the advantage that the costs of packaging are shared among the good die on the wafer.
A wafer-level cavity package for an image sensor can be achieved simply by applying a wafer-level picture frame of adhesive onto each die, attaching a glass wafer to cover the delicate micro lenses, and then sawing the assembly into individual die.
Since the die are encapsulated at the very first step of the assembly process, the micro lenses are protected from exposure to particles from the very beginning of processing following wafer manufacture. Particles produced during dicing and wire bonding processes can be removed more easily from a polished glass surface than from freshly formed micro lenses. In addition, any particles that do land on the glass cover and remain over the image sensor area are less noticeable in the electronic image because they are removed from the focal plane; a group of pixels of decreased brightness is visually much less obvious and less distracting than a single black pixel in an image. The assembly yield of covered image sensors is thus maximized, independent of sensor resolution and pixel size.
 Figure 3. Image sensor die with exposed bond pads on all four sides and a glass cover, fabricated using a “Shellcase CF” wafer-level process. |
To facilitate easy and rapid adoption, any new technology should ideally be backwards compatible with the one it replaces. What is required are image sensors that have been protected at the wafer level and that can be assembled into camera modules on an existing COB line. This requires the covered die to have exposed bond pads on all four sides and is accomplished by removing the glass from the scribe lane area while leaving the cover directly above the pixel array intact (Fig. 3). This operation is accomplished while the dies are still in wafer form.
Other benefits of covered image sensors include relaxation of the cleanliness standard required of the COB line, improved environmental protection for the optical area of the die, and the ability to perform optical testing at the wafer level prior to module assembly. By identifying optically good die prior to module assembly, this approach increases efficiency and reduces costs.
WLP technology achieves high assembly yields regardless of the image sensor resolution. COB assembly provides a flexible and low-cost method of die attach and interconnection. The marriage of these commercially proven technologies offers the prospect of reducing the cost of camera modules containing high-resolution sensors.
Acknowledgments
Shellcase is a registered trademark of Tessera Inc.
Giles Humpston received his BSc in metallurgy and his PhD in alloy phase equilibria from Brunel U., England. He is director of metallurgical technologies at Tessera, 3099 Orchard Dr., San Jose, CA 95134; ph 408/123-4567, e-mail [email protected].
Yehudit Dagan received her BSc in physics and her MSc in heat transfer engineering from Tel Aviv U., and her MSc in technology management from the Israeli branch of the Polytechnic University of New York. She is VP of marketing at Tessera Israel Ltd.