Pushing planar transistors to the limit using strained channel engineering
11/01/2006
The quest to satisfy the low-power and low-leakage requirements of portable/mobile consumer electronics is driving efforts to improve transistor performance. However, such performance enhancement cannot be achieved using classical scaling of transistor dimensions because leakage current will exceed standby power requirements.This article describes a number of channel mobility enhancement techniques that can be used to address this issue.
Portable, digital electronics and wireless communication markets have increased tremendously in the last five years, driving worldwide semiconductor sales in 2005 to $227.5 billion, with 2006 sales expected to rise 9.8% to $249.6 billion, according to the Semiconductor Industry Association. Consumers’ quest for lighter, more compact, and longer-lasting battery life has imposed more stringent power requirements on transistor operation. The semiconductor industry has, until now, maintained its historical doubling of chip functionality every two years by continually reducing transistor dimensions. As gate lengths approach sub-45nm dimensions and gate oxides approach 1nm, scaling becomes more challenging, and new material and device structures are required to overcome the fundamental physical limitations imposed by traditional semiconductor materials.
The obstacles to continuing the reduction of transistor dimensions can be traced to threshold voltage and gate oxide thickness that cannot be scaled at the same rate as supply voltage (Vdd) without leakage current exceeding stand-by power requirements for portable electronics applications. Thus, transistor scaling rapidly reduces the maximum gate overdrive factor, Cox (Vdd-VT) [1] or transistor drive current (Id), which is a measure of device/circuit performance. Moreover, higher channel doping concentrations and more abrupt, shallow source-drain junctions used to control short-channel effects at very short gate lengths result in carrier mobility degradation, increasing threshold voltage variation, junction leakage, and capacitance.
High-mobility channels
The conventional scaling approach is a trade-off between power and performance. In addition, portable electronic products with extended battery operation require that microelectronic chips operate at low Vdd and have low power dissipation or leakage. With the delay of high-k and metal gate solutions for the 65nm technology node, much attention has been focused on high-mobility channel engineering that exhibits increased inversion layer mobilities and higher carrier velocities in short-channel devices. High-mobility channel engineering can boost CMOS device drive-current without aggressively scaling transistor gate length or gate oxide thickness to meet the required performance at lower operating voltage, while also dramatically reducing active and static power dissipation.
High-mobility channels can be achieved by 1) process-induced strain (i.e., lattice-mismatch uniaxial strain); 2) biaxial strain virtual substrates; 3) modification of surface and channel orientation; or 4) selection of channel materials with high mobility and saturation velocities such as Ge, SiGe alloys, or III/V compound semiconductors.
By improving drive-current performance, strained-Si devices may provide a one- or two-generation boost in switching speeds while requiring minimal changes to device design for early market penetration. Such a technology may even mitigate the mobility degradation arising from the use of high-k gate dielectrics for gate leakage reduction.
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Enhancing carrier mobility can be achieved by several techniques using uniaxially strained Si using tensile or compressive stressors [2], biaxially strained Si on relaxed SiGe virtual substrates [3], or biaxially strained Si on insulator (SSOI). Innovation in maximizing the re-use of existing materials, tools, and device platforms has enabled the development of uniaxial stressors to boost both p-type and n-type channel devices in record time.
Uniaxial embedded SiGe stressors in the source/drain regions of the bulk pMOS devices were inserted into the mainstream at 90nm in late 2003 by Intel [2], and surely will be used as a p-type mobility booster for high-performance 65nm bulk or SOI circuits by many IDMs [4, 5].
Uniaxial strain
One novel approach for high-performance CMOS enhancement is the use of uniaxial strain for carrier mobility enhancement in which a significant stress (tensile or compressive) is imposed on the device in a preferred direction relative to the channel. The strain distribution is typically localized to affect only one type (“p” or “n”) of transistor. This is achieved either by stressor incorporation in selected areas, or by locally altering the film characteristics of an initially blanket stressor film.
Under strain conditions, semiconductor energy bands are shifted relative to each other, and band shapes are changed. When a state is reached with reduced inter-/intra-band scattering or with reduced effective masses, the carrier mobility is enhanced. The impact of strain on carrier mobility can be directly characterized with a piezoresistance model by measuring mobility characteristics of conventionally built devices subjected to an external mechanical stress. Much work has been accomplished in the characterization of carrier mobility, with results characterizing the impact of multiple factors such as device type and channel orientation.
The table shows piezoresistance results with the percentage of carrier mobility enhancement for every 100MPa tensile/(compressive) strain for bulk p/nMOSFETs with <110>/<100> channel orientation. The data is directional for proper uniaxial stressor design. For example, for pMOS with a <110> channel orientation, the highest mobility enhancement is achieved by adding compressive longitudinal strain while minimizing the stress in the width direction. However, for nMOS of the same orientation, tensile stress is desirable. The optimal stress configuration for CMOS is shown in Fig. 1a.
The use of stress to enhance CMOS performance, however, will increase process complexity and cost. The simplest approach utilizing existing manufacturing processes and tools will be the most desirable. Dual compressive and tensile contact etch stop layers (dESL) or interlayer dielectric (ILD) as a stressor have also proven to be viable solutions. Their rapid development times are due to their relative simplicity and re-use of existing manufacturing tools for further enhancing CMOS performance at sub-90nm technologies [3-6], especially when combined in a dual integration scheme [7-9].
Combining the stress sensitivities of <110> channel orientation for pMOS devices with optimized transverse and lateral boundary placement can enhance the dESL performance gains in conjunction with the poly pitch effect [9, 10]. Figure 1b shows a high-resolution TEM of the resulting dESL integration on a pMOS device with 70nm lateral boundary spacing. This particular TEM is from an integration where the compressive film is formed first, and the tensile film next.
As the <110> pMOS device can be enhanced dramatically with compressive stress in the lateral direction (parallel to current flow) pMOS also prefers tensile stress in the transverse direction (perpendicular to current flow), as shown in Fig. 1b. In dESL integration, this can be achieved by placing the boundary between the compressive and tensile films close to the pFET in the transverse direction. Furthermore, all of these geometry effects need to be accurately modeled to maximize product performance gain. Figure 1c contains the 1.2V Ioff-IDsat curves for nMOS and pMOS devices with a dESL integration combining high-stress films with +400MPa tensile and −650MPa compressive lateral channel stresses, respectively. More than 40% IDsat improvement was achieved for pMOS, but <10% IDsat gain was achieved for nMOS by implementing dESL stress.
Incorporating an epitaxial stressor layer in pre-recessed device S/D regions can form other uniaxial stressors. The epitaxial material has a different lattice constant compared to the substrate. When the atoms of the grown film are well aligned with that of the substrate, and there are no (or negligible) misfit dislocations, the mismatch of the lattice constants of the substrate and refilling materials induces stress to the channel, resulting in mobility enhancement. Epitaxial SiGe or SiC are the typical stressor materials in this case.
 Figure 2. 65nm strained pMOS: a) device structure and b) HR-TEM and Fourier transform diffractogram from S/D SiGe region in the device. |
As Ge has a 4% larger lattice constant (5.66Å) than that of Si (5.43Å), SiGe deposited on Si will undergo compressive strain. The S/D embedded SiGe (eSiGe) therefore induces the desirable lateral channel compression, while the S/D embedded SiC induces channel tension (because of the 3.56Å lattice constant of diamond), which enhances hole and electron mobilities and drive currents for the CMOS transistors, respectively. Many reports on pMOS S/D eSiGe stressors have been disclosed in recent years for bulk and SOI technologies. Ghani et al. reported that eSiGe for 90nm node bulk circuits were in production in late 2003 [2]. To couple eSiGe performance enhancement and SOI substrate benefits, Zhang et al. reported an eSiGe stressor for 65nm SOI. Figures 2a and 2b show the 65nm strained pMOS device structure and a HR-TEM with Fourier transform diffractogram from the S/D SiGe region, having at least 20% gain in IDsat [11]. Up to 45% IDsat gain can be accomplished by reducing the S/D eSiGe offset relative to the gate or by increasing the Ge concentration.
Figure 3a shows that coupling the eSiGe stressor with a compressive dESL stressor results in nearly linear enhancement. Greater than 50% pMOS drive current enhancement is demonstrated for eSiGe with dual ESL compared to the Si reference. The drawback of the uniaxial stressor is its strong dependence on geometry factors such as device width (Fig. 3b) and poly pitch or gate spacing (Fig. 3c), which are functions of density, as uniaxial ESL stressor performance is reduced with scaling. The study shows that the incorporation of eSiGe is important in order to maintain appreciable IDsat improvements for narrow device widths, while performance gains by dESL declines as device width and gate spacing decrease.
Other important benefits of the eSiGe stressor include its ability to retain hole mobility gains at high vertical fields, and to reduce device channel resistance (Rch) and extension resistance (Rex), which has significant impact on the short-channel transistor drive current. The Rex improvement in eSiGe is due to the ability to increase the active boron concentration in the S/D region using in situ doping, while a compressive ILD stressor reduces Rch to improve hole mobility.
Using a similar eSiGe process integration with an analogous mechanism for boosting n-type transistors, selective SiC epitaxially grown in the recessed S/D region imparts tensile stress in the n-type transistor channel. This approach has received much attention recently due to its similarity to the existing eSiGe module in manufacturing and the demonstrated potential for large performance gains up to 30% for n-type transistors due to electron mobility enhancement [12]. However the selective SiC process and precursor chemistry still need more development in order to achieve good quality epitaxial films with high substitutional C content as an effective tensile stressor.
There is no simple, single, and sustainable approach to boosting both n- and p-type transistor performance for more than 2 technology nodes without additional improvements. The impact of a uniaxial stressor on mobility gain is due to the proximity and volume, or the lattice spacing differential effect, as only 40-60% of the original stress from the stressor can be transferred to the channel, which has a proportional impact on the mobility gain. For example, a 3GPa compressive etch stop layer (cESL) film is needed to induce ~700MPa of compressive stress in the channel in order to boost p-type transistor performance by 40%.
Biaxial strain
To date, only biaxial tensile or compressive virtual substrates provide built-in stress of several GPa directly in the channel for enhancing the channel mobility. When a thin Si layer is grown pseudomorphically on a relaxed SiGe alloy buffer having larger lattice spacing than that of Si, the Si layer conforms to the SiGe template by expanding laterally and contracting vertically. This creates biaxial stress, which enhances the transport properties of the Si layer due to the altered band structure and electronic properties compared to unstrained-Si. Stress reduces inter-valley and inter-band phonon scattering and effective hole mass due to band warping and preferential thermal population of electron states with small effective transport mass. Improvements to both electron and hole mobilities by applying biaxial tensile-strained Si as a transistor channel have been demonstrated [13]. However, the fundamentally weak pMOS enhancement will pose scaling difficulties for global biaxial stressors in high-performance CMOS.
Although biaxial tension can produce modest hole mobility enhancement at low vertical effective fields, channel carrier sub-band splitting due to biaxial stress and its associated effective mass change [14] leads to an undesired enhancement sensitivity to the vertical effective field (Fig. 4a). The hole mobility enhancement under high effective gate fields is diminished and becomes negative when the fields are high.
Piezoresistance coefficients show that once the undesired tension along the channel is reversed (see table), strong pMOS enhancement would result. Moreover, the transverse tension along W should be preserved for pMOS performance [15]. A novel in-plane stress engineering approach achieves the desired CMOS stress configuration shown in Fig. 1a, which would be more difficult to achieve by using purely uniaxial or biaxial stressors [16].
Recently, the SSOI virtual substrate was developed by transferring a strained Si layer grown on a relaxed SiGe virtual substrate directly on insulator, which combines the benefits of mobility enhancement by biaxial tensile-strained Si channels with the advantages of SOI.
The interactions and optimizations between biaxial/uniaxial, stress
elaxation, and channel directions to obtain optimum performance gain for a 65nm CMOS device have been proven as shown in Fig. 4, with IDsat-Ioff nFET enhancement due to tensile etch stop layer (tESL) and SSOI, and short-channel pFET IDsat-Ioff enhancement due to selective uniaxial relaxation (SUR) and cESL for W = 1µm [17]. SOI vendors also have made impressive progress in improving quality, availability and SSOI substrate cost. Figure 5 illustrates the progress being made in threading dislocation density (TDD) reduction and pile-up (PU) elimination. These defects (inset) are potential yield killers, and also adversely affect device leakage, power dissipation, and die cost.
Conclusion
Achieving enhanced CMOS mobility is not simply achieved by incorporating biaxial strain originating in the substrate, and applying to both n- and p-type devices. Instead, biaxial tensile stress or uniaxial tensile stress for nMOS, and uniaxial compressive stress for pMOS, are used to generate maximum mobility enhancement. Uniaxial stressors have been employed primarily for boosting pMOS performance. It is more difficult to improve nMOS performance using the tensile stressor until a cost-effective and manufacturable selective embedded SiC process and a way to accomplish the integration of dual embedded S/D stressors are available. Such cost-effective solutions, however, entail changing the n:p ratio with technology scaling, and thus, extensive library and circuit layout changes are required. Enhancing both nMOS and pMOS performance to retain the same n:p ratio is desirable.
Interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor, and channel orientation have been optimized to achieve the desired stress configurations for enhancing both short-channel SSOI nMOS and pMOS devices. Significant progress has already been achieved in meeting the performance, power, and cost requirements for SSOI technology by collaborations between IDMs and substrate suppliers during the SSOI development and assessment phases. Moreover, extensive collaboration among IDMs, equipment and substrate suppliers, consortia, and universities is a critical factor in shortening development cycle-times, reducing development costs, and achieving early entry into mainstream production.
Acknowledgments
Additional co-authors of this paper are: T. White, Bo Sean, S. Zollner, D. Theodore, H. Desjardins, L. Prabhu, R. Garcia, J. Hackenberg, V. Dhandapani, V. Adams, S. Filipiak, S. Murphy, R. Rai, J. Conner, P. Montgomery, D. Eades, C. Parker, J. Hildreth, R. Noble, M. Jahanbani, L. Mathew, D. Pham, J. Mogab, J. Cheek, B. White, S. Venkatesan, Freescale Semiconductor; and I. Cayrefourcq, SOITEC, Bernin France.
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For more information, contact Bich-Yen Nguyen, Freescale Semiconductor, Technology Solutions Organization, 3501 Ed Bluestein Blvd., MD K-10, Austin, TX 78721; ph 512/933-5034, e-mail [email protected]; or contact Carlos Mazure, Soitec, Parc Technologique des Fontaines, 38190 Bernin, France; ph 33/0-476-92-7500, e-mail [email protected].