SEMATECH optimizes the gate stack with dual high-k and metal gate
10/01/2006
At the Symposium on VLSI Technology in June, SEMATECH reported on a new approach it has developed to meet ITRS requirements for low-standby power (LSTP) transistors for the 45nm technology generation. Called “dual high-k, dual metal gate” (DHDMG), the dielectric materials and metal gates to be optimized in separate processing steps.
 Schematic of the DHDMG CMOS process flow, with SEM and TEM photos after the complete separation of the first and second gate stacks. (Source: SEMATECH). |
Byoung Hun Lee, manager of SEMATECH’s advanced gate stack program, described the new process (see figure)-in which either the nMOS or pMOS regions can be formed first- to Solid State Technology. If, for example, the high-k dielectric material and metal electrode are deposited to form the nMOS region first, then the nMOS gate stack (both metal electrode and high-k material) is eliminated from the pMOS region of the wafer using a wet etch. A “fresh” electrode and high-k dielectric are then deposited for the pMOS region. “Then, using a similar process, the pMOS gate stack is removed from the nMOS region,” according to Lee. “This process allows nMOSFETs and pMOSFETs to be optimized independently, as well as allowing the use of different materials for each stack-for both dielectrics and metal electrodes, if necessary.”
Previous integration schemes tried to incorporate the same high-k dielectric for the nMOSFETs and pMOSFETs, but the nMOS and pMOS high-k dielectrics and electrodes could not be optimized independently, explained Lee. Problems arose with these methods, because “in the process of etching the metal electrode, the high-k dielectric was exposed to the wet etch, which resulted in pitting,” such as pinholes, he said.
According to Lee, the DHDMG process enables better control over gate profiles by eliminating the need to etch two different thicknesses of metal electrodes. “The different thicknesses of metal electrodes occur in integration schemes in which the second metal electrode is deposited on top of the first metal electrode,” he explained. The metal used to form the second metal electrode would be deposited on the entire wafer, yet a part of the wafer would also contain the other type of electrode (either nMOS or pMOS, as applicable). Dry-etching a stacked electrode and a single layer electrode on the same wafer is very difficult, so, “having a single layer for the pMOS and nMOS region, the thickness of the layers can be the same, even if the materials are different, so it is much easier to etch and get a clean profile,” Lee said.
SEMATECH is also working on simplifying the DHDMG process. By the end of this year, Lee anticipates that the team will have verified the feasibility and reliability of eliminating the hard mask that protects the electrode during the wet etch process. “If we are able to dry etch the metal and high-k materials together, then we can eliminate deposition of a hard mask and its removal, saving many steps,” he noted. “And dry etch allows for easier profile control.” -D.V.