Manufacturing challenges for immersion below 45nm
10/01/2006
With the introduction of the immersion technique into deep-submicron patterning, the semiconductor industry will manage to keep up with the scaling roadmap using refraction-based lithography for another two, hopefully three generations before switching to the most likely successor, extreme ultraviolet (EUV) lithography.
The extension of 193nm ArF-based lithography down to 45nm and below using “wet” immersion shows more promise than any other, more “exotic route,” and is rapidly gaining momentum in the industry. EUV lithography, e-beam, and nanoimprint lithography all suffer from a number of technical and economical challenges that have to be tackled before they can be inserted into manufacturing. In a sense, immersion litho is an evolutionary rather than a revolutionary approach, largely allowing an extension of the current infrastructure. Immersion litho uses the same light wavelength (193nm) as its predecessor, and thus benefits from the installed base of companies and technical staffs already familiar with the process. That is why immersion lithography is poised to be the next leading semiconductor patterning process for 45nm, 32nm and possibly even for the 22nm technology generation.
EUV lithography would be a prime candidate for printing the critical layers of 32nm half-pitch nodes and has extendibility to 22nm. But, at least for 32nm, it will not be ready in time for manufacturers to insert it into manufacturing. Many technological roadblocks still have to be removed, including the light source, resists, masks, defects, metrology, operation in ultra-high vacuum, etc. In addition, cost and related issues such as throughput limitations due to the patterning in vacuum will result in the fact that, most likely, we will have to rely on 193nm immersion litho down to the 32nm half-pitch.
Today, however, immersion litho is still in its exploratory phase, with a large number of issues to be solved first. While present 193nm immersion litho allows patterning at 45nm half-pitch and possibly even beyond, it is clear that it will be extremely difficult to do so, at least if single exposures using water as immersion liquid are targeted.
Although immersion lithography is theoretically possible, it will require high-refractive index fluids instead of water as the immersion liquid, an optical material for the last lens element with a higher index, and a very high-index photoresist. In particular, the development and the ROI model for the high-index optical material are considered potential roadblocks. Also the manufacturability of hyper-NA (NA>1) imaging, limits of chemically amplified resists, and defectivity requirements will remain challenging.
Topics to be investigated carefully will include the search for appropriate high-index fluids with the required specs and their effect on lithographic performance, the material compatibility, and the impact on defectivity. When using resolution enhancement techniques, lithographic performance will become critical at hyper-NA due to mask 3D effects. As a consequence, alternative mask stacks will have to be investigated, designed, and evaluated.
To meet stringent scaling roadmaps, especially of flash, extensive use of double-patterning techniques may also be required. If one considers double-patterning using (water) immersion lithography, 32nm half-pitches become feasible, but it remains questionable whether this is a cost-effective solution for some applications. Since no fundamental new infrastructure is needed, double-patterning could be the only option available in time for patterning the 32nm half-pitch node-but it is an extremely complex and costly solution. In particular, overlay remains a difficult issue and demonstration of manufacturability still remains to be seen.
Timely readiness for manufacturing remains key. Already for EUV, this will be a challenge, which is why IMEC’s lithography program now runs hyper-NA immersion, double-patterning immersion, and EUV in parallel, performing research on the 32nm node and beyond. A strong link with device research remains mandatory, and the advanced litho program is coupled tightly with the device programs for CMOS for advanced logic and also with the advanced memory program.
The 32nm challenge will be a tough one to meet, at least from the lithography side. It remains to be seen to what extent EUV will take over from 193nm immersion litho, and what effort and cost will be required to use EUV in manufacturing.
For more information, contact Ludo Deferm, VP, business development, IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; ph 32/1628-1880, e-mail [email protected].
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Ludo Deferm,
IMEC, Leuven, Belgium