Meeting future SDE requirements using co-implantation and RTA
10/01/2006
The requirements for the source/drain extensions of future devices are increasingly more demanding with respect to dopant activation, junction depth, and abruptness as semiconductor technology continues to scale [1]. Ultrashallow junction (USJ) technologies that are being explored to meet these demands include co-implantation of diffusion-retarding species with rapid thermal annealing (RTA). The shallow junction depths and reduced lateral diffusion produced by this technique are confirmed by two-dimensional scanning spreading resistance microscopy (SSRM) measurements.
Blanket wafer studies of junction depth and dopant activation are essential to the development of USJ processes such as co-implantation combined with RTA and the understanding of their physical mechanisms of diffusion retardation. However, electrical measurement of the impact of these improvements on devices, such as reduced gate/extension overlap capacitance or series resistance, is also necessary to verify that the observed blanket wafer benefits translate into actual device improvements.
Both blanket wafer characterization studies and device wafer parametrics are reported here for USJs formed by co-implantation with conventional spike anneal. Fluorine and carbon co-implantation with B+ for PMOS transistors and P+ for NMOS transistors, combined with conventional spike annealing, produce reduced junction depths and improved dopant activation and profile abruptness, as measured on blanket wafers and compared to similar implants without the co-implanted species. Device wafers show that the overlap capacitance is reduced, consistent with the shallower junction depths and reduced lateral diffusion, and that the improved dopant activation manifests itself in reduced series resistance and improved Ion values.
Experimental details
Blanket wafer and device experiments were carried out on 200mm Si wafers. In order to form the ultra-shallow source/drain extensions (SDE) with co-implants, a first step of Si or Ge pre-amorphization (PAI) was used. This was followed by a C or F implant and finally a dopant implant. These were B for PMOS extensions and P for NMOS extensions. On the device wafers, these extensions have been implemented into a conventional transistor flow, primarily with polysilicon gates on SiON gate dielectric but with Ni fully silicided (FUSI) gates [2] in some cases. The only significant modifications were the PAI step and C and F co-implantation. Channel and deep junction (HDD) implants only received slight modifications.
Dopant activation and damage annealing was done by a 1050°C spike anneal unless noted otherwise. The implants were carried out on an Applied Materials Quantum X implant system, while the activation spike anneal was performed on an Applied Materials Centura RadiancePlus. Chemical profiles were measured by secondary ion mass spectrometry (SIMS) using an Atomika 4500 instrument with a 500eV O2 analyzing beam. Two-dimensional profiles of activated carrier concentration were also obtained on selected samples by scanning spreading resistance microscopy (SSRM) [3].
Results and discussion
Figure 1 shows the benefits of combining Ge pre-amorphization and F or C co-implantation with 500eV, 1×1015 cm-2 B implants [4, 5]. The Ge implant energies ranged from 2-20keV, while the F was implanted at 10keV and the C was implanted at 4keV. Without a F or C co-implant, the boron diffuses considerably during the 1050°C spike anneal and produces a junction deeper than 40nm at a concentration of 1×1018cm-3 with a diffusion shoulder at a concentration of ~1×1020cm-3 and a sheet resistance of 435Ω/sq.
 Figure 1. SIMS profiles of boron as-implanted with Ge pre-amorphization and after 1050°C spike anneal with Ge PAI and F or C co-implant. |
The addition of co-implanted F significantly reduces the boron diffusion and creates a more box-like profile. The junction depth is only 30nm; the profile abruptness is improved to 4.5nm/decade; and the diffusion shoulder (which is indicative of the electrical activation) is increased to give a similar sheet resistance of 479Ω/sq. despite the reduced junction depth. Nevertheless, the effect of co-implanted C is especially striking, as the B profile is now much steeper and considerably less diffused due to the trapping of Si interstitials by substitutional C. The junction depth has now been reduced to 23nm; the abruptness is only 2.5nm/decade; and the concentration of the diffusion shoulder has increased to 2×1020cm-3 so that the sheet resistance is only slightly increased to 573Ω/sq.
 Figure 2. SIMS profiles of phosphorus as-implanted and after 1050°C spike anneal, with C co-implant, and with Si PAI and C co-implant. |
Similar to the improvements seen with C co-implant for B dopant profiles, Fig. 2 presents the implementation of the same concept for the case of the n-type dopant P [6, 7]. A P-only implant with an energy of 1keV and dose of 7×1014cm-2 activated by a 1050°C spike anneal has a very long diffusion tail due to transient enhanced diffusion (TED), a relatively high junction depth of 35nm at a concentration of 5×1018cm-3, and a moderate sheet resistance of 411Ω/sq.
When a 6keV, 1×1015cm-2 C co-implant is added with no pre-amorphization, the dopant activation (indicated by the P diffusion shoulder), sheet resistance (349Ω/sq.), and profile abruptness are improved, and the junction depth is slightly reduced to 30nm. Nevertheless, the Si+C+P case with an additional 25keV, 1×1015cm-2 Si pre-amorphizing implant, which results in an initial amorphous layer of around 60nm, shows a dramatically different profile. Here, the combination of a localized end-of-range (EOR) damage region coupled with a layer of substitutional C suppresses the interstitial-driven diffusion and very strongly affects the shape of the P profile, producing a box with a depth of 21nm and an abruptness of 3nm/decade. The P diffusion shoulder occurs at a high concentration of 4×1020cm-3, resulting in an excellent conduction layer with a low sheet resistance of 318Ω/sq.
Two significant transistor parameters affected directly by the USJ characteristics are the source/drain (S/D) resistance and the overlap capacitance. The S/D resistance is the total series resistance between the source and drain and includes the resistance of the source/drain extensions. Increasing the SDE dopant activation will reduce the S/D resistance and increase the transistor’s drive current (Ion) for a given drain voltage. The overlap capacitance is related to the area of the SDE under the gate. Reduced SDE lateral diffusion will decrease this area and the resultant capacitance. The delay time of an actual device, such as a ring oscillator, is proportional to CV/I, so lower overlap capacitance and higher Ion will lead to faster devices. Thus, future devices must have smaller overlap capacitance and lower series resistance, which can be obtained with reduced SDE lateral diffusion and higher dopant activation.
The device impact of the benefits of F and C co-implants for the B source/drain extension profiles is demonstrated in Fig. 3 and Fig. 4. The co-implanted junctions were activated with a spike anneal. Two spike anneal temperatures (1050° and 1030°C) were investigated. The benefit in dopant activation and S/D resistance with co-implants is highlighted in Fig. 3, where the S/D resistance is plotted as a function of the minimum gate length supported at a fixed Ioff of 60nA.
The blanket wafer results showed improved dopant activation with the F co-implant but a reasonably deep junction. Correspondingly, the F co-implanted junctions lead to lower S/D resistance, but the minimum gate length supported at fixed Ioff is larger than that for the BF2 conventional case. In contrast, C co-implanted junctions, which are much shallower and have greater dopant activation, produce improvements both in short-channel effects and S/D resistance.
The correlation between saturation on-state current corresponding to an off-state current of 60nA and overlap capacitance (Cov) for BF2 implants and F and C co-implants at various spike anneal temperatures is presented in Fig. 4. The lower spike anneal temperature of 1030°C leads to less lateral diffusion and smaller overlap capacitance for both F and C co-implants. In addition, the slightly deeper junction obtained with a 1050°C anneal results in lower S/D resistance and increased Ion. An F co-implant produces higher Ion without any reduction in Cov, which is consistent with the improved dopant activation and fairly deep junctions seen on blanket wafers. However, 10% Ion gain is obtained with slightly reduced overlap capacitance for C co-implant and 1050°C spike anneal, while a large reduction in Cov accompanied by a small increase in Ion is achieved with 1030°C anneal. These results highlight the suppression of lateral boron diffusion under the gate and the simultaneous improvement in the S/D resistance by the use of C co-implants.
 Figure 5. Two-dimensional SSRM images of activated carrier concentration for a BF2 implanted device (left) and a C co-implanted device (right) after spike anneal. |
Figure 5 shows two-dimensional SSRM images of activated carrier concentration for a BF2 implanted device (left) and a C co-implanted device (right) after spike anneal. The ability of C co-implant to reduce the boron vertical diffusion is evident, as the SDE vertical junction depth is dramatically reduced from 38nm to 14nm, and even the HDD junction depth is decreased from 90nm to 82nm. In addition, C co-implant strongly suppresses the boron lateral diffusion such that the gate/SDE overlap is shrunk from 22nm to 10nm, which is consistent with the electrically measured reduction in Cov.
Conclusion
Blanket and device wafer studies have been conducted to verify the benefits of USJs formed by co-implantation with conventional spike anneal. C co-implant improves the junction depth, profile abruptness, and concentration of the diffusion shoulder (which is indicative of the dopant activation) for both PMOS and NMOS transistors. Devices with C co-implanted SDEs exhibit better short channel effects and S/D resistance, consistent with the one-dimensional benefits. Finally, SSRM images confirm that the lateral boron diffusion of both the SDE and HDD is greatly reduced with co-implant.
Acknowledgments
Additional authors of this paper are: V. Parihar, F. Nouri, E. Collart, S. Thirupapuliyur, and R. Schreutelkamp (Applied Materials, Sunnyvale, CA); A. Falepin, E. Augendre, and T. Noda (Matsushita Electric Industrial Co., Ltd., Japan), and W. Vandervorst (IMEC, Leuven, Belgium). Quantum X, Centura, and Radiance Plus are registered trademarks of Applied Materials.
References
1. The International Technology Roadmap for Semiconductors, 2005, www.itrs.net.
2. K.G. Anil et al., “Demonstration of Fully Ni-Silicided Metal Gates on HfO2-Based High-k Dielectrics as a Candidate for Low-Power Applications,” Proc. of Symp. on VLSI Technology, pp. 190-191, 2004.
3. P.C. Eyben, S. Severi, R. Duffy, B. Pawlak, W. Vandervorst, “Analysis and Optimization of New Implantation and Activation Mechanisms in Ultra Shallow Junction Implants using Scanning Spreading Resistance Microscopy (SSRM),” to be published in Proc. of MRS Symposium C, Spring 2006.
4. H. Graoui, M. Foad, V. Moroz, “Source and Drain Extension Formation Using Carbon Co-implantation for PMOS Devices,” Proc. of Ultra-Shallow Junctions 2005, p. 346, 2005.
5. B.J. Pawlak, T. Janssens, T. Brijs, W. Vandervosrt, E.J.H. Collart, S.B. Felch, N.E.B. Cowern, “Effect of Amorphization and Carbon Co-Doping on Activation and Diffusion of Boron in Silicon,” to be published in Appl. Phys. Lett., August 2006.
6. E.J.H Collart, S.B Felch, B.J. Pawlak, P.P. Absil, S. Severi, T. Janssens, W.Vandervorst, “Co-implantation with Conventional Spike Anneal Solutions for 45nm NMOS Ultra-Shallow Junction Formation,” J. Vac. Sci. Technol. B 24, 507, 2006.
7. B.J. Pawlak, R. Duffy, T. Janssens, W. Vandervorst, S.B. Felch, E.J.H. Collart, N.E.B. Cowern, “Suppression of Phosphorus Diffusion by Carbon Co-doping,” Appl. Phys. Lett., 89, p. 062102, August 2006.
For more information, contact Susan Felch at Applied Materials, 974 E. Arques Ave., M/S 81280, Sunnyvale, CA 94085; e-mail [email protected].