A process window-based approach to mask optimization
10/01/2006
Different performance and wafer-yield criteria apply to different types of integrated circuits, and the masks for those circuits may need to be optimized to achieve maximum value of production. An approach that takes the entire process window into account-rather than using only pattern fidelity at nominal process conditions-can reveal which areas of the design are robust, and which will present problems at the edges of the process window. This technique can help reduce the amount of over-design needed to compensate for poor control of wafer printing and can provide valuable information about the weakest areas of a given design, to increase profit per wafer.
Microprocessors and general-purpose standard cell ASICs are examples of ICs that have extremely different performance and wafer-yield criteria. Microprocessors are speed-sorted and priced according to clock speed; the fastest are highly valued by the market. The incentive is to design for optimal performance at nominal process conditions, even if only a fraction of the total die per wafer achieves that performance. In lithographic terms, even if many of the die are not imaged at optimal focus and exposure, and thus do not perform at peak speed (so that they must be sold at a lower price), the die that are imaged optimally do operate at peak speed and actually determine the bulk of the profit per wafer.
In contrast, general-purpose ASICs are sorted according to pass/fail speed criteria that are less demanding, and all die that pass command the same price, which is much lower than for microprocessors. The incentive is to over-design, so that nearly all die on a wafer pass the specification even if the lithographic and other process conditions are not optimal. For example, at 130nm geometries, ASIC speeds of over 400MHz are attainable, although the “pass” requirement of the market into which many ASICs are sold is as low as 250MHz. This speed margin allows for variability of the semiconductor manufacturing process including, increasingly, lithography.
The majority of semiconductor masks are computed using only pattern fidelity at nominal process conditions as the metric for success. This places the ASIC manufacturer at an economic disadvantage; to serve that market, mask generation technologies that use “process window” (PW) instead of “fidelity at nominal” as a metric can reduce the amount of over-designing to compensate for poor control of printing across the wafer (and from wafer to wafer). Further, PW-aware mask computation can provide microprocessor manufacturers with valuable information about the weakest parts of a given design.
Two optimizations
Inverse lithography technology (ILT) [1] can operate in either the fidelity at-nominal or the PW-aware mode. The merit function employed during mask computation can emphasize pattern fidelity either at nominal exposure and defocus (ED) only, or at several points in the ED plane. Figure 1 shows one example where different mask patterns resulted from the different criteria even though the target design, mask technology, and illumination conditions were the same [2].
The minimum feature size is 80nm and the minimum spacing is 100nm for this polysilicon pattern. A clear-field, 6% attenuated phase-shift mask was used with 193nm illumination, NA= 0.85, and an annular light source with σi/σo = 0.5/0.85. In Fig. 1a, the mask was designed for better fidelity at nominal ED, while the Fig. 1b mask was designed for a better process window. The target for both is shown in Fig. 1c. The nominal-targeted mask pattern in a) exhibits more fine structure and lower bias than the PW-tuned mask in b). Corners of the target are accentuated so greatly in a) that at the location of the inner corners of the T structures of the original layout, the mask pattern is “broken” (disconnected); this broken structure allows maximum fidelity near inner corners and better image matching on straight parts of the design (gates), to minimize poly-active alignment tolerance. Part of the simulated image at nominal ED corresponding to a) is shown in Fig. 1d as a red contour overlaid on the design intent (blue). The image contour of d) deviates from the target by no more than 1nm up to a distance of 25nm from inner corners.
In contrast, the mask tuned for expanded process window, shown in Fig. 1b, is more biased and exhibits less fine structure; this results in images across the ED window that vary little from the target, as shown in Fig. 1e. Three contour images are shown in magnification in Fig. 1f: the red contour is the image at nominal ED; the blue contour is the image at nominal focus and 7% dose variation; and the gray contour is the computed forward image at nominal exposure and 100nm defocus, all shown overlaid on the desired pattern. The image contour at nominal conditions follows the target less closely than for the mask of Fig. 1a; it is within 3nm of the target pattern up to a distance of 45nm from inner corners. Hence, a looser gate width spec (by 2nm) is required for Fig. 1b as compared to Fig. 1a, which results in better image stability through dose and focus.
Local bias
While masks are generally computed with a single center dosage (i.e., threshold) in mind, they are often biased to adjust to a new threshold. This biasing is performed globally across the mask, in general practice. In deep subwavelength lithography, a global bias may not suffice due to diffraction and interference effects. What if it is desired to find a mask that prints well across several thresholds, so as to improve exposure latitude? Will the result be a simple bias?
Figure 2 shows the results of a study on whether a global bias is indeed correct, and whether simultaneous optimization produces a simple averaged mask. Fig. 2a shows the design target, with 90nm minimum feature size and 92nm minimum space. (Only a portion of a 4-fold symmetric repeating cell is shown.) A CoG mask was used with 193nm illumination, NA = 0.75, and annular σi/σo = 0.5/0.85.
Three masks were computed with only a single target threshold each: thresholds of 0.23, 0.27, and 0.30 of flood intensity. These are chosen to be symmetric about a central nominal threshold of 0.27 and overlaid in Figs. 2b and 2c in different shades of blue. The lowest threshold (light blue), the middle threshold (medium blue), and the highest threshold (dark blue) result in masks that differ by an approximately constant bias in isolated regions; however, in areas where the design features lie close to each other, the mask computed at one threshold may overlap or even cross over designs for other thresholds.
Lastly, a mask was computed that is optimized to print well at all three doses (thresholds of 0.27±12.5%); it is overlaid in orange with the target and the medium-threshold single-dose mask (blue) in Fig. 2d. This multidose mask is not a simple average of the three single-dose masks, as can be seen from the magnified inset in Fig. 2e. In isolated areas (see arrow), the masks are nearly coincident, but in dense areas they are not.
Scaling to full-chip designs
Full-chip process window computation is time-consuming if the same number of exposure and defocus points are used as in Bossung plots. It can be more useful to look at process-window corners and have pass-failure reports just at selected ED points: nominal, ± maximum defocus at nominal exposure, ± maximum exposure error at best focus, plus four other sites within the process window. Using Luminescent’s implementation of ILT, we ran a moderately sized portion of a 65nm design (about 200µm on a side).
At each process corner, the system reports work units that passed all tolerance specifications for the simulated image when compared to the target. Figure 3a shows the result; each colored rectangle consists of arrays of rectangular inspection units ~10µm on a side. Those shown in white have some site within them that has failed the edge placement error criteria under the ED condition. For nominal exposure and defocus, all portions of the design passed. The number of failing units increases with deviation from nominal, with different inspection areas failing under different conditions. There is a contour on the ED plane where all work units have met the specification at the sampled process “corners.” The area defined by those corners is the full-chip process window. Figure 3b overlays arrays from the four extreme conditions with “failing” inspection areas shown as clear. Where the image is green, everything has met spec. The colors correspond to conditions in which the indicated units have fulfilled the specification at one or another extreme and the clear or white areas indicate regions where failure is consistent and might benefit from re-design.
With this information available, the economic viability of a design may be increased. For ASIC manufacturers, knowledge of the exposure latitude can give more direct estimates of the number of workable die per wafer. Regions of the design that are not robust to this ED variability may be examined further to ascertain the design practices or off-the-shelf IP blocks that are less robust [3]. For microprocessor manufacturers, design rules and practices that limit component speed may be identified and corrected, leading to increased profit per wafer.
Conclusion
Computing a mask that takes into account the variation of exposure and focus [4] has clear economic value. As shown in this article, masks computed for good image fidelity at multiple exposure and focus points are not simple geometric combinations of masks that are computed to optimize printability at a single ED point. An approach that takes the entire process window into account can reveal which areas of the design are robust and which will present problems at the edges of the process window.
With simple treatments, masks like those shown in Figs. 1 and 2 can be made manufacturable and yield the expected result in silicon [5, 6]. Adoption of this approach requires more extensive calibration of the semiconductor process [7] and new mask computation tooling.
References
1. D. Abrams, L. Pang, “Fast Inverse Lithography Technology,” 31st Internal Symposium of Microlithography, Proc. of SPIE, Vol. 6154-55, San Jose, CA, Feb. 2006.
2. Y. Liu, D. Abrams, L. Pang, A. Moore, “Inverse Lithography Technology Principles in Practice,” 25th Annual BACUS Symposium on Photomask Technology, Proc. of SPIE, Vol. 5992-39, Monterey, CA, Oct. 2005.
3. B. Lin, et al., “Inverse Lithography Technology at Chip Scale,” 31st Internal Symposium of Microlithography, Proc. of SPIE, Vol. 6154-41, San Jose, CA, Feb. 2006.
4. Yong Liu, Anton K. Pfau, Avideh Zakhor, “Systematic Design of Phase-shifting Masks with Extended Depth of Focus and/or Shifted-focus Plane,” Proc. of SPIE, Vol. 1674-2, San Jose, CA, March 1992.
5. P. Martin, “Manufacturability Study of Masks Created by Inverse Lithography Technology (ILT),” 25th Annual BACUS Symposium on Photomask Technology, Proc. of SPIE, Vol. 5992-35, Monterey, CA, Oct. 2005.
6. L. Pang, et al., “Laser and E-beam Mask-to-Silicon with Inverse Lithography Technology (ILT),” 25th Annual BACUS Symposium on Photomask Technology, Proc. of SPIE, Vol. 5992-21, Oct. 2005.
7. A. Borjon et al., “Through-process Window Resist Modeling Strategies for the 65 nm Node,” 25th Annual BACUS Symposium on Photomask Technology, Proc. of SPIE, Vol. 5992-19, Oct. 2005.
Andrew Moore received his PhD from Caltech. He is the VP of corporate marketing, business development, and a scientist at Luminescent Technologies Inc., 2471 E. Bayshore Road, Suite 600, Paolo Alto, CA 94303; ph 650/433-1011; fax 650/960-3954; e-mail [email protected].
Daniel Abrams received his bachelors at Stanford and his PhD at MIT. He is CTO and cofounder of Luminescent, a scientist, and an entrepreneur who founded two successful software companies prior to Luminescent.
Linyong (Leo) Pang received his MS in computer science and PhD in engineering at Stanford. He is the VP of product marketing and business development at Luminescent Technologies.
Yong Liu received his PhD from U.C. Berkeley. He is director of marketing and applications at Luminescent Technologies.