Issue



Extending 193nm immersion with hybrid optical maskless lithography


09/01/2006







Immersion-based optical lithography techniques at 193nm have made great progress and are viewed by many as an option for the 45nm node. But options for the 32nm node are uncertain. EUV is one possibility. However, critical technological issues regarding light sources, masks, resists, and other must first be solved. The only other viable option appears to be enhancing 193nm immersion by multiple exposures. The key question for this option is what type of multiple exposure solution is most economical and practical to implement. This article discusses a specific type of multiple exposure optical approach we refer to as hybrid optical maskless lithography (HOMA).

M. Fritze, T. M. Bloomstein, B. Tyrrell, M. Rothschild, Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA

In the HOMA approach, all critical features are imaged using a maskless template provided by a dense interferometrically generated grating. Such a grating can provide feature resolution and process latitudes superior to mask-based gratings. A second conventional optical trim exposure customizes the grating into patterns useful for semiconductor ICs. This process can be thought of as a high-resolution maskless carrier pattern with information added by a lower resolution optical modulation pattern. A simple example of such a process is shown in Fig. 1, where an interference grating is shown with some lines erased by a subsequent optical trim exposure.


Figure 1. Exposures performed in the same resist prior to development for: a) a 45nm half-pitch grating pattern imaged with MIT LL’s 157nm interferometer system; and b) a trimmed grating pattern combining interferometric grating exposure with 248nm projection trimming exposure to “erase” a number of grating lines.
Click here to enlarge image

The HOMA method is a hybrid combination of high-resolution maskless (optical interferometric) and lower resolution optical projection. Both exposures are capable of very high throughputs. Key questions for such a proposed technology include the specifics of decomposing typical semiconductor patterns, implications for the IC design process, and scalability to the 32nm node and beyond.

Extending 193nm immersion lithography

It is becoming increasingly clear that 193nm optical lithography will need to be extended further than anticipated, which implies the use of increasingly more aggressive resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and phase shift masks. The increasing use of such methods has accelerated a trend towards lithography-friendly designs [1, 2]. In practice, this means that common circuit geometries are becoming more regular and symmetrical. Additionally, critical gate features are being restricted to one orientation, and allowed pitch values are severely limited.

The HOMA approach builds on these trends by recognizing that most common circuit patterns can be formed from a simple grating template pattern that is trimmed by an additional exposure. Contacts can also be handled in such a way by crossed grating exposures, although a negative tone resist is required in this case. The key for practical implementation is the method of decomposition of desired patterns into trimmed gratings, the process integration for fabrication, and the implications for circuit designers of such an approach.

Implementing HOMA

We have studied HOMA implementation of a number of typical 32nm node circuit cells using Sigma-C simulation [3]. Some results of these simulations are shown in Fig. 2. These simulations assume a dense grating with high contrast first exposed with an interference patterning tool at 32nm half-pitch. This may be accomplished using an immersion interference printer operating at either 157nm [4] or 193nm [5].


Figure 2. Simulated a) 32nm node SRAM gate pattern using 193nm trimming with NA=1.1; b) AND cell using 193nm trimming with NA=1.1; and c) 32nm node contact array using 193nm trimming with NA=1.1.
Click here to enlarge image

An important result of this work was the realization that the required trim resolution was one to two nodes simpler than the grating resolution, enabling 193nm projection systems designed for the 45 and 65nm nodes to be used. Process latitudes were limited by the optical trim step, but were still in excess of 0.2µm depth-of-focus (DOF) at 10% exposure latitude (EL). Although OPC is expected to improve the process latitudes further, we did not use it in these simulations. A new type of proximity effect must be dealt with here that is related to the lower resolution trim exposure affecting adjacent critical features. Our simulations have shown that the HOMA method has the potential to meet the needs of the 32nm node with an all-optical lithography method. Further extensions of this method may be possible with the use of high-index immersion trim, optimized RET trim, or e-beam array trimming.

We have also performed some initial experimental feasibility studies of the HOMA method [6]. For this work, we used a 157nm interference-based patterning system custom built at Lincoln Laboratory for the grating exposures [7]. The projection trimming was provided by a 248nm stepper. We investigated two types of hybrid exposure approaches. The first was a single resist method, where both exposures were performed in the same resist film prior to development. For this part, we used an in-house resist sensitive to both 157nm and 248nm wavelengths. The second was a dual-resist method where the grating was first exposed in one resist film and hard-baked, followed by a second resist coat and the trim exposure. The final etched pattern is the geometric sum of both resist layer patterns.


Figure 3. Etched SEM images from: a) and b) a HOMA process combining a 45nm half-pitch interference grating exposure with a binary mask 248nm projection exposure; the coarse and fine features were transferred into the same silicon layer by RIE etching. c) A cross-sectional SEM image from this same process.
Click here to enlarge image

Some experimental results are shown in Fig. 3. Note the summation of the high-resolution grating and lower resolution trim patterns and how well they transferred into the underlying silicon by the reactive ion etch (RIE).

We also explored the use of a nonoptical trim step to enhance the resolution of HOMA and simulate the performance of an immersion 193nm trim tool not available to us. For this work we combined our optical interference grating with e-beam trimming. The results of this work are shown in Fig. 4. The high-resolution pillar patterns could be changed to contacts with the use of a negative tone resist. An important conclusion here is the potential to use maskless technologies such as e-beam arrays or programmable optical masks together with a HOMA approach. This has the potential to provide an all-maskless HOMA implementation with much greater throughput than other currently envisioned maskless technologies.


Figure 4. SEM images of a HOMA process combining a 45nm half-pitch interference grating with e-beam trimming: a) a 39nm pillar array and a b) DRAM pattern.
Click here to enlarge image

Interference-based double exposure has the additional advantage of being more easily extended to sub-32nm half-pitch grids than projection-based grid formation. While projection systems will be available at 193nm for the foreseeable future, interference can be performed at the shorter wavelength of 157nm, enabling finer pitch. In fact, at Lincoln Laboratory we have demonstrated 27nm half-pitch gratings [8] and even 22nm half-pitch gratings [9] using immersion interference at 157nm.

Making use of the HOMA method for semiconductor lithography will certainly have implications for the design process. All critical features, gates, contacts, and metal will need to be placed on a coarse grid. Recent work has considered such placement restrictions and concluded that layout density is not necessarily impacted [10, 11]. Coarse grid restrictions may help simplify the design process by making layouts RET-compliant by construction without requiring complex RET corrections at the end of the design cycle.

Conclusion

We have proposed a new type of multiple exposure lithography known as hybrid optical maskless lithography. We have shown that this method has the potential to meet the needs of the 32nm node and possibly beyond. It is an all-optical approach combining the advantages of maskless and projection lithography while still maintaining very high throughput. The simplified geometries involved should also help ease the burden on RET-compliant circuit design.

Acknowledgments

The authors would like to thank Susan Cann, Sandy Deneault, Nikolay Efremow Jr., Theodore Fedynyshyn, Dennis Hardy, Donna Lennon, Mike Marchant, and Steven Spector for their contributions to this work. This work was sponsored by the Defense Advanced Research Projects Agency under Air Force Contract FA8721-05-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and do not necessarily represent the view of the US government.

References

  1. L. Liebmann, D. Maynard, K. McCullen, N. Seong, E. Buturla, M. Lavin, J. Hibbeler, Proc. SPIE, 5756, 1 2005.
  2. L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, et al, Proc. SPIE, 5379, 20, 2004.
  3. M. Fritze, B. Tyrrell, T. Fedynyshyn, M. Rothschild, P. Brooker, Proc. SPIE, 5751, 1058, 2005.
  4. M. Switkes, M. Rothschild, J. Vac. Sci. Technol., B19, 2353, 2001.
  5. R.H. French, H. Sewell, M.K. Yang, S. Peng, D. McCafferty, W. Qiu, R.C. Wheland, M.F. Lemon, L. Markoya, M.K. Crawford, J. Microlithography, 4, 31103, 2005.
  6. M. Fritze, T.M. Bloomstein, B. Tyrrell, T.H. Fedynyshyn, N.N. Efremow Jr., D.E. Hardy, et al., J. Vac. Sci. Technol., B23, 2743, 2005.
  7. T.M. Bloomstein, P.W. Juodawlkis, R.B. Swint, S.G. Cann, S.J. Deneault, N.N. Efremow Jr., J. Vac. Sci. Technol., B23, 2617, 2005.
  8. T.M. Bloomstein, T.H. Fedynyshyn, I. Pottebaum, M. Marchant, S. Deneault, M. Rothschild, J. Vac. Sci. Technol., submitted 2006.
  9. T.M. Bloomstein, M.F. Marchant, S. Deneault, D.E. Hardy, M. Rothschild, “22nm Immersion Interference Lithography,” accepted by Optics Express for publication.
  10. B. Tyrrell, M. Fritze, D. Astolfi, R. Mallen, B. Wheeler, P. Rhyins, P. Martin, J. Microlith., 1, 243, 2002.
  11. J. Wang, A.K. Wong, E.Y. Lam, J. Microlith., 4, 13001, 2005.

M. Fritze received his PhD in physics at Brown U. and is a staff member at Lincoln Laboratory, Massachusetts Institute of Technology, 244 Wood Street, Lexington, MA 02420; ph 781-981-2626, email [email protected].

T. M. Bloomstein received his ScD in electrical engineering from MIT and is a staff member at Lincoln Laboratory, Massachusetts Institute of Technology.

B. Tyrrell received his BSE in electrical engineering from the U. of Pennsylvania and MS in electrical engineering from MIT and is an associate staff member at Lincoln Laboratory, Massachusetts Institute of Technology.

M. Rothschild received his PhD in optics from the U. of Rochester and is leader of the Submicrometer Technology Group at Lincoln Laboratory, Massachusetts Institute of Technology.