Improving workfunction control of metal gate electrodes
09/01/2006
Next-generation MOSFET devices require the introduction of metal gate (MG) electrodes for further performance increases. A key challenge to implementing MGs, however, is the selection of a metal with the appropriate workfunction. The correct choice is critical because the effective workfunction of a gate electrode (and hence MOSFET threshold voltage) is critically controlled by the interface between the gate dielectric and metal electrode. This paper describes a novel route to workfunction control using the modification of the interface polarization layer by careful deposition of both the dielectric stack and the metal gate, followed by a high temperature treatment. It is shown that the electrostatic potential at the interface can be perturbed by a polarization layer and that this can be engineered at a monolayer (ML) level.
Luigi Pantisano, Tom Schram, Marc Heyns, IMEC, Leuven, Belgium; Barry O’Sullivan, Stefan De Gendt, Guido Groeseneken, IMEC and Katholieke U.’s ESAT, Leuven, Belgium
One of the most important parameters is the effective workfunction (Φeff) of the gate, which is in contact with the dielectric. The Φeff affects the device flatband voltage (Vfb) and thus controls the threshold voltage (Vt) of a MOSFET. Until now, Φeff modulation has been realized by:
- either changing the dielectric [1] or the MG material and/or by affecting their composition [2],
- introducing impurities into the MG, and
- depositing metal laminates.
Nevertheless, the trend commonly reported consists of a systematic shift of the Φeff towards mid-gap (4.4-4.8eV) after thermal treatments above 800°C.
Contrary to the common belief, the interface between the gate electrode and the dielectric plays a dominant role in the definition of Φeff. This has recently been illustrated by exposing ruthenium metal gates in contact with different dielectrics (SiO2 and HfO2) to oxidizing
educing ambient [3]. This report further suggests that altering the electrostatic potential at the gate electrode/insulator interface may be the key to steer the Φeff to a desired value.
In the present work, we further demonstrate that the interface between a gate dielectric and metal gate determines the effective workfunction and thus, the MOSFET Vt. The interface electrostatic [4] is perturbed by the introduction of a polarization layer (built from oxidized transition metals) that can be engineered at the monolayer (ML) level. Our observations are consistent with previous reports of the impact of monolayers of hafnium oxide (HfO2) on the barrier height and the corresponding Φeff values at the interfaces of SiO2 with polycrystalline silicon [5].
By carefully depositing both the dielectric and the metal in an ultrahigh vacuum (UHV) molecular beam epitaxy (MBE) chamber (and thus avoiding the introduction of impurities), we demonstrate that the polarization of the interface is modified upon the application of a high temperature treatment, offering an easy approach to control the Φeff. This concept is further exploited by gauging the impact on the interface electrostatics of a submonolayer of a spin-deposited dielectric material.
Experiments
High-k dielectric stacks featuring HfO2 or La2Hf2O7 (LHO) were considered. These dielectrics were deposited either by atomic layer deposition (ALD) or by MBE on 200mm Si wafers. A 10nm in situ or ex situ TaN metal gate was deposited by sputtering and capped with 70nm TiN. Overlapping MOS capacitors were processed in a conventional flow. Some of these capacitors were made with the high-k deposited on a SiO2 layer whose thickness is varied across the wafer by HF etching (slant etch) [6].
Incorporating “guest” impurities at the high-k/metal interface by a spin-on contamination technique was also studied. MOS capacitor structures with either thermally grown slant-etched SiO2 or atomic layer deposited HfO2 covered slant-etched SiO2 were used as the gate dielectric. Strontium (Sr) impurities were introduced in the SiO2 or HfO2 gate dielectric by spin-on of a Sr nitride solution. Via ALD, a 10nm-thick TiN layer, which was then capped with 70nm of sputtered TiN, formed the metal gate. The gate deposition was preceded by a degas at 400°C for 10 min. The Sr concentration was estimated to be ~3 × 1013atm/cm2 from total x-ray fluoroscopy (TXRF) measurements. Several activation anneal temperatures were evaluated; these anneals were followed by a forming gas anneal (FGA) treatment. In some experiments, Φeff was extracted using C-V measurements.
The composition of the dielectric has a significant impact on the gate Φeff. For the same integration scheme, Φeff evolves from 3.9-4.5eV in the presence of a TaN gate in contact with an MBE LHO and HfO2 dielectric, respectively (see the C-V curves reported in Fig. 1). Vfb appears to be quasi independent of the dielectric thickness, suggesting that the contribution of the fixed oxide charge is negligible, and the observed effect is related to the MG/oxide interface.
Monolayer dielectric workfunction control
Since the interactions responsible for the Φeff changes are believed to be limited to the MG-dielectric interfacial layer, Φeff can be tuned by a controlled deposition of a ML of a “guest dielectric/impurity” on top of a host dielectric. This concept is illustrated in Fig. 2, which shows the MOSFET gate insulator comprising the main (host) part and the guest overlayer deposited to tune the MG Φeff. The host dielectric, HfO2 for instance, can be engineered to guarantee both high carrier channel mobility and a low leakage current, as well as to attain the desired equivalent oxide thickness (EOT) specifications. The guest dielectric and the MG can be engineered for optimal (dual) Φeff and MG etchability.
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The proposed Φeff tunability is demonstrated by results shown in Fig. 3, by the deposition of 2 ML of LHO on top of a host HfO2 layer. Note that the deposition is done in an UHV-MBE chamber to ensure optimum process control. Without activation anneal, the Φeff of TaN is 4.5eV and remains unperturbed by LHO deposition. However, after activation annealing the Φeff is reduced by ~200mV in the case of the 2 ML guest LHO film (Fig. 3). Figure 3 also suggests that the Φeff reduction is enhanced in the case of in situ MG deposition. Direct measurement of the energy barrier between the TaN Fermi level and the oxide conduction band using electron IPE (not shown) also supports the finding regarding a lowering of the barrier due to the impact of the LHO interlayer.
Submonolayer dielectric WF modulation
Figure 4 illustrates the Φeff shift caused by the presence of strontium impurities on SiO2 and HfO2 host dielectrics. We observe an increase in the Φeff of 0.21 and 0.04eV when the strontium impurities are introduced at the SiO2/TiN and HfO2/TiN interfaces, respectively. Opposite to the LHO case, the presence of a submonolayer of strontium oxide leads to the increase of the device workfunction.
We believe that a large part of this change in Φeff is bound to a “local variation” of the interface polarization/electrostatic due to the difference in topology/coordination of the deposited guest with respect to the “host” dielectric. To provide some insights, we modeled the gate/host dielectric system in an approach similar to a two-plate capacitor in which the charges of the capacitor are atomic partial charges arising from the electron transfer occurring during the formation of the metal/dielectric oxygen bonds. We computed the partial atomic charges of all the atoms in the system (qi) [7], following the electronegativity equalization concept developed by Sanderson and formulated by J. Smith [8].
In the presence of an oxygen-rich medium, the electron transfer occurs from the impurities to the neighboring oxygen atoms, leading to an increase of the interface electrostatic potential and to a shift of Φeff by ~+0.13 and +0.10eV when placed in contact with TiN/SiO2 and TiN/HfO2, respectively.
Conclusion
The interface between gate dielectric and metal gate critically determines the effective workfunction Φeff and therefore, the MOSFET threshold voltage. The interface electrostatics [4] can be effectively tuned by a polarization layer, which can be engineered at the monolayer or submonolayer level. The interface polarization layer is modified after high-temperature treatment and offers a means to control the Φeff. Several materials were analyzed. To meet the effective workfunction targets of 4.2eV and 5.3eV, a larger shift is needed with respect to our current findings. It is believed that the interface polarization layer can be tuned through the thickness of the guest dielectric or the differences in the electronegativity of the materials used. This tuning enables further stack engineering either by introducing other highly polarizing species or by further increasing the polarizing-species content in the dielectric.
Acknowledgments
Additional authors of this work are Geoffrey Pourtois and Amal Akheyar. The authors would like to acknowledge Riber SA, France, for the deposition in the MBE chamber and D. Brunco (Intel) and L-Å. Ragnarsson (IMEC) for useful discussion.
References
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- J. Smith et al., “A New Method of Estimating the Atomic Charges by Electronegativity Equilibration,” J. Chem. Edu., Vol. 67, p. 559, 1990.
Luigi Pantisano received his MS and PhD in electrical engineering from the U. of Padova. From 2000 to 2001, he worked at Bell Labs on the plasma damage impact on RF devices. Since 2001, Pantisano has been a research scientist working on the reliability and characterization of high-k dielectrics for CMOS applications for the Reliability Group at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; ph 32/1628-1457, e-mail [email protected].
Tom Schram received his PhD in engineering at the U. of Brussels (VUB) and is senior scientist at IMEC.
Marc M. Heyns received his PhD in electrical engineering from Katholicke U. (KU) Leuven, Belgium, and is a research fellow at IMEC. He is a professor in the electrical engineering department (ESAT).
Barry O’Sullivan received his BSc in applied physics from the U. of Limerick, Ireland. He received his MEngSc and PhD in microelectronics from the National U. of Ireland, Cork. O’Sullivan is currently completing a post-doctoral research position in the department of chemistry, KU Leuven, at IMEC.
Stefan De Gendt received his masters and PhD in chemistry from the U. of Antwerp, Belgium and is a principal scientist working at IMEC in the field of high-k and metal gates. He is a part-time professor in the department of chemistry, KU Leuven.
Guido Groeseneken received his MSc in electrical and mechanical engineering and his PhD in applied sciences, both from the KU, Leuven. He is manager of reliability research and the post-CMOS nanotechnology program within IMEC’s core partner research program. He is a professor in the electrical engineering department (ESAT) at KU Leuven.