The ConFab
08/01/2006
Speakers discuss how to manage the new economics of chipmaking
The ConFab-sponsored by Solid State Technology and our parent company, PennWell-brought together the leading semiconductor manufacturing executives for three days of dialogue and collaboration this past May in Las Vegas. For those unable to attend, we have prepared a Special Online Staff Report that summarizes the key presentations and discussions that explored the most challenging economic issues facing the industry today. To read the report, go to SST’s web site: www.solid-state.com. Click on the August issue cover and scroll down to the Special ConFab Report.
The Next Ten Years
IBM’s Meyerson: “Scaling is dead;” long live collaborative innovation
 Bernard Meyerson |
The semiconductor industry needs to usher in a new era of “collaborative innovation” to push beyond the limits of classical scaling and achieve new advances in information technology price performance. proposed Bernard Meyerson, IBM fellow, VP strategic alliances, and chief technologist at IBM’s Systems and Technology Group. -Phil LoPiccolo, Editor-in-Chief, Solid State Technology
New Business Models for Manufacturing
At a crossroads: Can fabless companies address rising costs and avoid consolidation?
With costs soaring to support nanometer-era IC production, has the fabless industry finally come to the point where widespread consolidation is imminent? Or, can fabless companies continue to operate much as they have for the last 15+ years? Daniel Gitlin, VP of semiconductor technology for Xilinx, presented ideas for a new business model for fabless companies. -Ed Korczynski, Senior Technical Editor, Solid State Technology
How an IDM can maximize vertical integration advantages
 Michihiro Inoue |
Foundries aren’t the only ones that are adopting new business models. Michihiro Inoue, executive engineer with Matsushita Electric Industrial Co. Ltd.’s semiconductor company, described how Panasonic-the brand by which Matsushita Electric Industrial is generally known-has developed strategies and business models aimed at vertically integrating its chipmaking with its appliances and electronic equipment. -Bob Haavind, Editorial Director, Solid State Technology
SMIC poised to ride the China wave
Charles Huang, SVP of SMIC’s Shanghai operation, described the general strategies foundries can take to produce next-generation semiconductor technology and outlined his company’s plans to exploit the burgeoning demand for ICs in China-now the world’s largest regional IC market. -Phil LoPiccolo
Business models go both horizontal and vertical
A ConFab panel on business models for manufacturing revealed that while some companies are becoming more vertically integrated, others are pushing toward a more horizontal structure. -Bob Haavind
Addressing R&D, mask costs also top foundry concerns, says SMIC exec
Charles Huang, SVP of Semiconductor Manufacturing International Corp.’s (SMIC) Shanghai operation, proposed strategies foundries can take to overcome some of the fundamental challenges they face in moving to next-generation semiconductor manufacturing. -Phil LoPiccolo
EDA design issues: “Not broken, but changing”
 Raul Camposano |
We are in the midst of fundamental changes in the way chips are designed regardless of the designing company’s business model, according to Raul Camposano, CTO and GM of Synopsys’ silicon engineering group. -Ed Korczynski
The economics of sub-45nm manufacturing processes
Simplifying the economics of sub-45nm chipmaking for equipment suppliers
 |
Relating important application trends to process tool requirements, Masayuki Tomoyasu, director of development and planning for Tokyo Electron, Ltd. (TEL), analyzed a number of emerging and potential collaboration modes that might improve results within budget constraints. -Bob Haavind
Chartered goes “nano” without breaking the bank
Chartered Semiconductor’s collaboration with industry leaders such as IBM, Samsung, Infineon, and AMD has given the Singapore foundry access to leading-edge design, process, and manufacturing technologies. The result has been a boon to the foundry’s ability to drive yields and ramp rates, said SVP of fab operations, K.C. Ang. -Debra Vogler, Senior Technical Editor, Solid State Technology
Manufacturing best practices: Lessons from other Industries
Solectron follows Toyota’s map down the road to manufacturing efficiencies
For Solectron, a vastly improved manufacturing operation was achieved by following in the steps of Toyota, renowned for its streamlined production systems, and deploying a combination of lean manufacturing and “Six Sigma” methodologies, according to Mark Onetto, EVP of worldwide operations. -James Montgomery, News Editor, Solid State Technology
What do semiconductors and NASCAR have in common?
One key aspect of Solectron’s lean Six Sigma manufacturing production program is to employ a so-called Jidoka style of improvement, a counterintuitive technique that entails stopping a production line when a defect is discovered, and not restarting it until the problem is fixed. -Phil LoPiccolo
Process control: To err is human...but so is learning
 Thomas Edgar |
Thomas Edgar, from U. Texas/Austin’s department of chemical engineering, showed where the semiconductor industry can take advantage of new manufacturing efficiencies through APC, such as batch fault detection, multiscale modeling, and design-for-manufacturing. -James Montgomery
Boeing approaches right-sized manufacturing model
Michael Herscher, leader of Boeing Commercial Airplanes’ lean enterprise office, related his company’s efforts to streamline manufacturing dating back to the early 1980s. -James Montgomery
The transition to 450mm
Disconnect marks 450mm wafer debate
 Scott Kramer |
A ConFab session on 450mm wafers provided a multifaceted look at a sharp split that has developed in the industry. Peter Silverman, Intel Fellow, stated the need for a 30% cost/cm2 reduction every 10 years to follow Moore’s Law, while ISMI director Scott Kramer noted that won’t happen even with a 450mm transition by the ITRS goal of 2012. And don’t expect equipment suppliers to dig deep to fund the major 450mm transition effort, since more productive tools means fewer tools needed, and no clear return on R&D investments, warned Applied Materials’ Mark Pinto. -Bob Haavind
How lessons learned from the 300mm conversion also apply to the productivity Roadmap
 ISMI economic model: Industry productivity will log the historical rate early in the next decade based on ITRS characterization. (Courtesy of ISMI) |
A detailed economic model suggests that industry productivity will lag historical trends early in the next decade, slowing the decline in cost/transistor, unless new initiatives get underway to reverse this trend, reported Scott Kramer, director, International Sematech Manufacturing Initiative. -Bob Haavind
Cost-effective Lithography
Pushing “Moore” out of lithography
 Double patterning enables extension of proven lithography by >1 node. (Courtesy of ASML) |
Peter Jenkins, VP of marketing for ASML, described lithography options and challenges at the 32nm half-pitch, including those such as no clear consensus on the part of IC manufacturers with respect to the kind of lithography needed at 32nm (although EUV is preferred for 22nm half-pitch). -Debra Vogler
Litho costs won’t limit Moore’s Law, but technology is the key
 Advanced mask manufacturing cost at the 65nm node. (Courtesy of Dai Nippon Printing Co.) |
null
 Kazou Ushida |
Kazuo Ushida, Nikon Corp., compared the array of future litho contenders with the options in 1999-157nm F2, e-beam, ion projection, and x-ray have been replaced by EUV, ArF immersion, and double-patterning-and concluded that it looks like “deja vu all over again.” -Bob Haavind
Deflating the mask cost bubble
 Naoya Hayashi |
Inspection, writing, and materials add up to more than 80 percent of the costs of masks at the 65nm technology node, according to Naoya Hayashi, senior researcher and GM at Dai Nippon Printing Co. Ltd.’s electronic device operations. He proposed several solutions to the problem of increasing mask costs at leading-edge chipmaking nodes. -Debra Vogler
Solutions to the R&D Challenge Panel Discussion
Can an open R&D ecosystem weather the advancing “perfect storm”?
 Simon Yang |
Simon Yang, senior VP and CTO of Chartered Semiconductor Manufacturing, joined the chorus calling for greater support of an industry-wide “open ecosystem of R&D” to deal with the impending funding crisis. -Phil LoPiccolo
With deeper industry collaboration, everyone wins, says Samsung exec
 Ho-Kyu Kang |
Ho-Kyu Kang from Samsung Semiconductor called for further industry collaborations involving high-risk (and high-return) investments and multiple nodes, and involving partners with multiple business models. Suppliers will benefit if the chipmaker partner can be a “teaching” customer. -Ed Korczynski
Maximizing R&D efficiency industry-wide
 Mark Pinto |
The semiconductor industry and its suppliers have had to cope with exploding R&D costs, a broadening in scope, and the need for continuous innovation with a number of strategies, according to Applied Materials’ Mark Pinto, CTO and SVP, new business and new products group. -Debra Vogler
Inside IBM’s partnerships: Albany set to start 32nm work
 Harry Calhoun |
Harry Calhoun, IBM’s VP of strategic relationships, technology and IP, presented an overview of IBM’s partnerships to pool resources to help develop new manufacturing capabilities, and soften the overall impacts of R&D expenses required for the next technology node. -Ed Korczynski