Intel describes CMOS tri-gate integration
08/01/2006
Intel Corp. recently presented results of its work with CMOS tri-gate transistors, citing its successful integration of high-k gate dielectrics, metal gate electrodes, and strained silicon to offer considerably lower leakage and consume much less power than today’s planar transistors. The devices could become the basic building blocks for future microprocessors beyond the 45nm node, the company explained, in a pre-briefing before displaying the full results of its work at the VLSI Symposium in Hawaii on June 13.
The company hasn’t made a decision yet as to whether this technology will go into production at the 32nm or 22nm nodes-it is also working on other technology options for those nodes. If the company adopts this particular tri-gate technology, it would be utilized across all microprocessor product lines, according to Mike Mayberry, director of components research and VP of Intel’s technology and manufacturing group. The way the device would be optimized (speed, power, or in-between) would depend on whether it was to be used for a desktop, server, or mobile application.
Mayberry noted that the company is nowhere near having a test chip with a billion transistors (with this architecture), but said they have made small arrays of these devices and the next steps will be to make increasingly larger arrays in order to understand the manufacturing “gotchas.” If the company decides to use this transistor architecture for high-volume manufacturing, it would take a couple of years of development time-i.e., until somewhere around the end of the decade, plus or minus a year.
Intel’s tri-gate structure, first announced in September 2002, surrounds the channel on three of four sides (see figure). Using high-k and metal gates improves both on and off current. High-k enables a more efficient coupling of the field into the channel-i.e., making it easier to switch the current on or off, so the device can run both faster and cooler at the same time, noted Mayberry. Adding strain improves the mobility, and also results in faster, cooler operation.
 X-dir. and Y-dir. cross-sections of PMOS trigate, with SiGe raised source/drains. |
Overall, less power is wasted by the integration of these three technologies. Compared with today’s 65nm transistors, this integrated tri-gate transistor can offer speed increases up to 45% (when optimized for speed) than what’s available at the 65nm node, or if the user wants to optimize for power, the standby current can be reduced 50×, according to Mayberry. Another mid-way choice is a 35% reduction in total power at constant speed when optimizing both active and off current. “You can pick a different operating point depending on the choices of whether you want a battery-powered device, in which case you would probably pick a very low-standby current, or whether you want a little more speed,” noted Mayberry.
Comparing the manufacturability of the tri-gate transistor to planar transistors is somewhat difficult, but regarding the very difficult task of manufacturing CNTs, Mayberry noted that, “The problem is, no one knows how to put them [CNTs] precisely in a particular spot except by moving them around one at a time.” Even test chips have a billion devices in them, he said, “so trying to make CNTs go precisely in a billion different places is, today, an insurmountable challenge… It is something we are continuing to research, but it’s a much longer time horizon.”
Mayberry further acknowledged that the company has experimented with trying to make an ideal transistor-one that has a gate completely surrounded by a very thin channel. To put a gate underneath the fin (in the tri-gate structure), Mayberry explained that you would have to tunnel underneath, and deposit a very high-quality insulating layer as well as a very high-quality, precisely tailored conductor. “We don’t have the tunneling equipment developed yet,” he said. “If we had a way to do that, then we could make that ideal device, but there’s simply no way to do it at this point in time.”
One of the etch profiles Intel used while researching the tri-gate device was notched at the bottom-it’s the beginning of the tunnel underneath, said Mayberry, adding that Intel saw substantial yield problems with that approach. “We’re in the business of making billions and billions of transistors, so, we look at a lot of things in research, but the things that go into development are the things that can be made manufacturable,” he said. “Today, it would not be manufacturable, but that’s not to say we won’t continue to look at things like that in research.”
Surface preparation, selecting the right combination of materials to put on the surface, the flow (temperature, ramp, combination of steps), etc. all matter, but Mayberry acknowledged that the most important is probably the choice of metal for the gate. The integration work was done entirely in-house. The company did not disclose details about what it used for a high-k gate dielectric and metal gate electrode. Intel “has literally done thousands of experiments to find the right combination of materials,” said Mayberry, although he indicated that the high-k material is Hafnium-based. -D.V., J.J.M.
Report from IITC: Future interconnects could include low-k air gaps, carbon nanotubes
The 9th annual International Interconnect Technology Conference in Burlingame, CA, again brought together hundreds of the world’s leading semiconductor manufacturers, equipment and materials suppliers, and research centers for three days of comparing notes and competing for bragging rights.
Among the highlights: detailed information on likely 45nm dual-damascene Cu/porous-low-k (PLK) integration, and the possible use of cost-effective dielectric “air-gap” large structured pores instead of random nano-pores to provide comparable electrical and mechanical results.
IITC participants also provided a glimpse into what may be next for chipmaking technologies. Applied Materials, Crolles2Alliance/LETI, IBM/Stanford, IMEC/Philips/ASM, Sony, and Toshiba all showed visions of 32nm node dual-damascene Cu/low-k interconnects. Plus, IMEC looked at Cu contacts for the 22nm node, and Fujitsu showed substantial progress in developing manufacturing processes to grow carbon nanotubes (CNT) as on-chip conductors.
Researchers from IMEC, along with Neocera and Intel (and ASM Japan which provided the low-k material), examined various 65nm dielectric integration schemes with a particular focus upon plasma etch processes for dual-damascene process flows. Using surface acoustic wave (SAW) frequency shifts, researchers could detect dielectric damage due to different etch chemistries. Depending upon the particular etch-chemistry and whether the etch process may be tuned to induce sidewall polymers, the as-deposited low-k material (k ≈ 2.5) varied from 2.3 to well over 3.5 in k value. Absorption of -OH radicals is a major concern, since it may be irreversible and can result in a “lossy dielectric.”
The Crolles2Alliance members showed their best results from CMOS 45nm SRAM test structures. They use ~2.5k PLK (with ~0.8nm average pore diameter) for both via and line levels, along with a thin metal barrier. While ~6% of the line cross-section is needed for the 8−10nm thick PVD barrier at 180nm, ~20% of the cross-section would be taken up by the same barrier by 45nm; consequently, 5−6nm thick ALD will be used. With an overall goal of doubling the interconnect density compared with the 65nm node, more hierarchy is imposed-lower levels with the tightest 130−140nm pitches, middle levels with 280nm pitch, and top levels with “fat” 0.8µm wires.
Usui-san from Toshiba’s Center for Semiconductor R&D discussed 32nm node interconnect formation, including a self-forming manganese silicon oxide (MnSixOy) barrier layer. Starting with dual-damascene trenches and vias, they deposit a 60nm thick alloy of Cu and Mn (40%), ECP fill with Cu, anneal at 250°C, then standard Cu CMP. The anneal step results in the formation of a ~2nm thick MnSixOy barrier layer at the interface between the low-k dielectrics and Cu. An important advantage of this process flow is that no barrier forms at via bottoms, reducing resistance by ~70% (shown on via chain tests).
Matsushita presented on “Air Gap Exclusion” using an additional lithography step, then SiO2 deposition to form pinch-off air gaps, SiO2 CMP, and finally blanket FSG deposition. By excluding large gaps degradation of planarity is avoided, while excluding small gaps prevents interlayer via shorts. The final structure demonstrated ~2.4 keff within the narrowest lines of local interconnects. Models show that this should be extendible to the 32nm node.
Researchers from Georgia Tech presented an invited paper on the theoretical limits of on-chip interconnects using carbon nanotubes (CNT) as conductors. For global interconnects, large multiwall CNTs offer the best conductivity, while bundles of single-wall CNTs provide the lowest delay for local interconnects. However, for <1µm lengths, Cu offers conductivities higher than either single-wall or multiwall CNTs.
Shintaro Sato from Fujitsu presented data on CNTs grown inside vias using catalyst particles. Bundles of multiwall CNTs were grown on Co particles by thermal CVD using C2H5 at milliPascal pressures. The current best results of ~10 CNTs (assuming ~7nm diameter) grown per 40nm diameter via result in only ~30% filling of the via volume. Thus, there is plenty of room to enhance the growth probability and to nearly fill the vias, which theoretically would provide lower resistance than tungsten.
Spectral photo-response (SPR) of interconnects is a newly discovered metrology technique that can characterize chemical composition, strain, defectivity, and air gaps in interconnects down to 22nm spacing (theoretically). Nondestructive and highly sensitive, the technique compares the leakage current under illumination-using a standard meander-comb test structure-to the dark leakage current. -E.K.
Novel vacuum chamber moves with the wafer
New Way Air Bearings, Aston, PA, has created a new “vacuum chamber stage” demo system which could have application in lithography, ion implant, mask-writing, and metrology processes requiring high precision in deep vacuum. Essentially, instead of putting a precision stage into a vacuum, the vacuum is put into the precision stage-so the chamber volume is little more than the size of the wafer, and all mechanical linkages are outside the chamber (see figure).
Methods to keep the mechanization outside of the vacuum chamber in conventional designs include linear and rotary contact seals, rotary Ferro-fluidic seals, and expanding and contracting bellows. Air-bearing structures have also been used to support some sort of a moving member through an aperture in the vacuum chamber wall. However, all such large vacuum chambers tend to have problems with particle generation, component out-gassing, or even simply the large surface areas of chamber walls.
 Novel vacuum chamber design cross-section, showing the minimal vacuum volume that moves with the wafer chuck. |
In contrast, this novel small process-chamber design moves with the wafer chuck and is held under vacuum with porous air-bearing technology (see figure). Unlike conventional orifice air bearings, porous media controls the airflow across the entire bearing surface through millions of holes in the material, resulting in more consistent air pressure distribution and the ability to create a vacuum down to ~10-8 torr. The very small chamber volume results in minimal pump-down time, requiring relatively smaller and less costly vacuum pumps, and theoretically less expense to build and support systems in manufacturing.
The chamber air bearing surface-pumped grooves bear directly on the plate to which the optics, ion source, or electron source would mount. Since the stage itself would be guided by its topside, running directly on the underside of the base to which the energy source is bolted, the structural loop would be reduced to the thickness of the 2D plate as opposed to that of a large 3D vacuum chamber. Guidance of the stage would be achieved with an annular air bearing separated from the vacuum section of the stage by differentially pumped groves.
This technology could provide strong advantages for immersion lithography, since the differentially pumped vacuum grooves could be used to keep the liquid physically constrained above the wafer during processing. Many reported problems with immersion lithography involve peeling resists, bubbles, and particulates that seem to be induced by the movement of the wafer into and out of the liquid. Liquid flow though the chamber for filtering and/or replenishment can occur through the main “vacuum” ports. -E.K.
Mentor tool offers hyperscaled DRC and model-based verification
Design-rule check (DRC) used to involve simple “go/no-go” checks, but simple compliance is no longer sufficient to account for the variety and complexity of nanometer-era manufacturing processes. To ensure high yield in nanometer-era chips, designers need statistically valid yield analysis based on physically verified models.
Addressing this need, Mentor Graphics has released a new DRC tool, “Calibre nmDRC,” as part of its new fifth-generation Calibre nm platform. Promising order-of-magnitude speed improvement for the same price, the tool integrates elements such as critical-area-analysis (CAA) and critical feature identification to provide real yield analysis as part of DRC. The product is currently in beta-tests with 30−40 customers, and should be officially released in 3Q06.
Calibre nmDRC determines the location of the most significant yield improvement opportunities, providing graded yield metrics by issue, cell, window, etc. The new software assesses the weighted greyscale of features that fail to meet recommended rules, and compares them to CAA particle sensitivities, such that the designer can evaluate both in the same deck and perform trade-off analyses.
The new software has been re-architected to allow hyperscaling to use shared memory processor systems as well as distributed rack systems in the most efficient manner possible. Designers can thus get the most out of current investments in design hardware (such as existing Linux clusters), and see runtime improvements more than double. Still, the new code drops into designers’ existing CAD environment without disruption.
Dynamic results visualization and incremental verification means that cells/blocks and other fundamental design subsets can be handled in parallel, so that debugging can start for some cells while others are still being checked. Combined with faster checking due to the hyperscaled software engine, incremental verification allows dramatically faster iteration on a timescale of hours instead of days.
The underlying Calibre nm Platform uniquely reads all open data formats, including GDSII, OpenAccess, Milkyway, LEF/DEF, and OASIS. Integrated into third-party tools, the database interface automates layer mapping, back-annotates DFM optimizations into the design database, and does not require disk space to save the GDSII data for every iteration. Also, changing from Standard Verification Rule Format (SVRF) to the higher-level Tcl Verification Format (TVF) for the coding language simplifies rule scripting and maintenance-the code to describe a recommended rule for prioritizing metal line widths is reduced from 509 lines of SVRF to just 64 lines of TVF. -E.K.