Integrating dual workfunction metal gates in CMOS
08/01/2006
As MOSFET scales below 45nm, conventional SiO2 cannot sustain equivalent oxide thickness (EOT) and leakage current requirements set in the International Technology Roadmap for Semiconductors (ITRS), due to the limitation of physical-thickness scaling, and high tunneling current [1]. Dual metal gate CMOS integration requires several wet etch processes to separate two different metal gates within transistors on the same wafer. Integration schemes as well as wet etch chemistries must be developed to completely remove the first metal gate without damaging the underlying gate dielectric. Hardmask material to selectively mask the first metal gate must be chosen carefully, since the hardmask is removed when the gate dielectric is exposed in certain integration schemes. This paper will introduce various integration schemes for fabricating dual metal gate CMOS field-effect transistors (FETs).
H f-based high k has been proposed as the most promising material to replace conventional SiO2, owing to its reasonably high-k value, thermal stability with the Si substrate, and acceptable reliability [2, 3]. Unscalable poly depletion necessitates a metal gate instead of the conventional poly gate [4, 5]. In order to achieve n and pMOSFETs on the highly doped substrate, two different metal gates are needed whose workfunction is close to the conduction (~4.1eV) and valence-band edges (~5.2eV) of the Si substrate for n and pMOSFETs, respectively. Even though extensive amounts of metals and their compounds have been studied to achieve target workfunctions, no industry consensus on the material has been established. In addition to identifying material, integrating two different metal gates into a single wafer is another critical challenge for the success of metal gate technology.
Comparing dual workfunction methods
Several methods have been published for integrating dual workfunction gate technology into the CMOS process (Fig. 1). These include various systems of interdiffusion [6-9], nitrogen implantation [10, 11], fully silicided (FUSI) metal [12-14], and DMG metal 1-etch-metal 2 methods [15, 16].
Interdiffusion. Dual metal interdiffusion systems selectively alloy the metal gate layer to achieve suitable workfunction values for nMOS and pMOS gates. Interdiffusion can use titanium/nickel (Ti/Ni) [6], hafnium/molybdenum (Hf/Mo) [7], ruthenium/tantalum (Ru/Ta) [8], or platinum/tantalum (Pt/Ta) [9] systems.
 Figure 1. Examples of dual metal gate CMOS integration schemes using a) interdiffusion method, b) FUSI method, and c) metal 1-etch-metal 2 method. |
The interdiffusion system deposits the first metal layer over the dielectric, followed by a layer of second metal (Fig. 1a). The second metal is then selectively removed from the nMOS (or pMOS) area, depending on the workfunctions of the first metal and the interdiffused metal. A subsequent thermal anneal or conventional S/D activation anneal is applied to interdiffuse the remaining second metal with the first metal in the pMOS (or nMOS) area. The interdiffusion can cause a second metal element to pile up at the interface between the metal and dielectric interface, or compound formation can set the desired workfunction.
An advantage of dual metal interdiffusion is that the gate dielectric is not exposed during the process. However, the dual metal composition must be strictly controlled because it determines the gate workfunction (and hence Vt). In areas where the second metal is removed, the remaining unary (unalloyed) metal tends to react with the dielectric and diffuse into the channel region, presenting performance and reliability issues. Finally, the dual metal interdiffusion method presents the challenge of gate-etching two different metal compounds on the same wafer.
Nitrogen implantation. This technique uses a single-metal layer selectively implanted with nitrogen to alter the workfunction in the one area relative to the other. The TiN implantation method deposits an n-depleted TiN layer followed by a resist mask and selective implantation of nitrogen in the nMOS area [10]. The workfunction of the n-rich TiN (nMOS) is lower than that of the n-depleted TiN (pMOS), producing a Vt shift of ~110mV. The MoN implantation method deposits an oriented Mo (110) layer, followed by masking and selective implantation of nitrogen in the nMOS area [11]. In this case, higher implant energy produces a greater workfunction reduction, with a shift of ~250-420mV depending on the implant energy.
Like interdiffusion, the nitrogen implantation method does not expose the gate dielectric and is simple and compatible with conventional CMOS processes. Gate etch is also easier in the implantation method because the implanted and nonimplanted metals etch at the same rate. The drawback to nitrogen implantation: it does not produce enough Vt shift for conventional CMOS devices, so it may be more appropriate for multiple Vt technologies for system-on-a-chip (SoC) applications and tunable dual workfunction technology for ultra-thin body silicon-on-insulator (SOI) devices with undoped channels. Other elements (e.g., Si, F) can also be used to alter the workfunction on certain metal gates.
The FUSI method has the advantage of being compatible with the conventional CMOS process flow. However, FUSI produces an inadequate workfunction separation: ~4.3-4.9eV on a SiON dielectric, ~4.4-4.8eV on HfSiON. The process window is very narrow for the phase-control method. In addition, an increase in EOT and reliability degradation due to chemical reaction between high-k and poly gate still exist in the FUSI approach.
Metal 1-etch-metal 2. The M1-etch-M2 method uses an intermediate wet etch between the deposition of two gate metals, as shown in Fig. 1c. S. Smavedam et al. [15] reported a method depositing TiN over an HfO2 dielectric followed by an oxide hardmask, which is then selectively removed from the nMOS area using a photoresist mask and etch. A wet etch then removes the TiN exposed by the oxide hardmask removal, and an HF clean is used to remove the remaining oxide hardmask. Now, only the pMOS dielectric is capped by TiN, and the nMOS dielectric is exposed. Next, a layer of TaSiN and a polysilicon capping layer are applied overall. This process produces a TiN/HfO2 interface for the pMOS gate stack and a TaSiN/HfO2 interface for nMOS.
We also reported a similar process [16] that first deposits TaSiN over the HfO2 dielectric. In this case, a TEOS oxide hardmask and wet etch are used to selectively expose the pMOS dielectric. After the hardmask is removed, overall layers of Ru and TaN are applied in sequence, producing a TaSiN/HfO2 interface for the nMOS gate stack and a Ru/HfO2 interface for pMOS.
The M1-etch-M2 method is very flexible in terms of selecting nMOS and pMOS gate metals to produce the desired workfunction. The method presents two critical challenges, however. First, the high-k dielectric is exposed during the first metal wet etch and hardmask removal, so the metal and hardmask must be etched with chemicals that do not attack the high-k dielectric. Second, the thickness and composition in the resulting pMOS and nMOS stacks are different, which presents a significant challenge during the dry etch of the gate stack.
The appropriate wet-etch process for the deposition-etch-deposition method depends on the metal, hardmask and dielectric wet etch rate for a given process. In particular, the dilute HF solution used to remove a TEOS oxide hardmask has little effect on a HfO2 dielectric, but vigorously attacks HfSiON. However, an amorphous silicon (a-Si) hardmask is readily etched with a NH4OH solution, which has little effect on either HfO2 or HfSiON dielectrics.
Wet etch results
Figure 2a compares HfO2/TaSiN gate stacks produced with and without a wet etch process. The TaSiN and TEOS hardmask removal results in ~0.8Å EOT loss, caused primarily by TaSiN removal etch. The slight EOT decrease results in a 3.5× increase in gate leakage current density (Jg), indicating that TEOS oxide hardmask removal is compatible with HfO2 dielectric. Similar to HfO2, HfSiON/TaSiN gate stacks with and without a wet etch process result in ~0.6Å EOT loss when a-Si hardmask is used (Fig. 2b). The slight EOT decrease results in a 3.3× increase in Jg, indicating that a-Si hardmask removal is compatible with a HfSiON dielectric. There is some concern that the first metal wet etch can undercut the hardmask. However, the undercut distance can be no more than the metal layer thickness, typically 10nm. The current 45nm design rule requires ~100nm of isolation space and another ~100nm between the gate and isolation space (Fig. 3), so there should be plenty of margin between the actual gate area to be defined by the gate-stack etch and the edge of the first metal gate defined by metal wet etch, even though metal undercut occurs.
As mentioned previously, the M1-etch-M2 technique presents a challenge during the gate-stack dry etch because gate thickness and composition are different for nMOS and pMOS. This challenge can be managed by using metals with identical etch chemistry for the two layers, for example, TiN for nMOS, and TaSiN for pMOS. These two metals can be etched at the same time. A small amount of over-etch is required, but it has been shown that the etch can stop safely on the high-k layer if an appropriate high-k dielectric is used and the dry-etch chemistry is selective enough.
The conventional M1-etch-M2 DMG method, as shown by several teams including Sematech, presents several remaining issues. The high-k dielectric in the second-metal area is exposed during selective removal of the first metal and hardmask, so the high-k dielectric in this area can be damaged significantly if the material is susceptible to the wet-etch chemical. Also, the differing metal gate thickness between nMOS and pMOS narrows the gate-stack dry etch process margin; where the metal gate is thinner, the dry etch can break through the high-k dielectric into the Si substrate. Also, the second metal layer can produce overlayer or intermixing effects on the first metal area, affecting gate workfunction and dielectric EOT. Finally, although the metal workfunction depends heavily on the high-k composition, the conventional method allows only one dielectric composition for both nMOS and pMOS metals.
To address these issues, we are pursuing two solutions. First, we can deposit the metal layers separately for nMOS and pMOS, so that no intermixing can occur; this also simplifies subsequent gate-stack etching by minimizing the difference in metal gate thickness. Second, we can separate the dielectric deposition so that different high-k compositions can be used for nMOS and pMOS, such that the high-k deposition is protected during subsequent etch processes.
In this scheme, the second high-k and metal gate deposition is followed, after the first metal gate and high-k layers are selectively removed. The second metal gate and high-k layers are also subsequently removed selectively from the area where the first high-k and metal gate remain (Fig. 4). Sematech has demonstrated this dual high-k and dual metal gate (DHDMG) CMOS with ~10% additional process steps (up to BEOL Metal 1) without compositional intermixing.
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Conclusion
We have reviewed technology options for implementing dual metal gates on the same wafer, identifying current issues and possible solutions. Among others, the M1-etch-M2 method can achieve desirable final Vt once appropriate high-k and metal gate materials are chosen, although issues remain. Separate control of high-k and metal gate on the nMOS and pMOS areas could resolve these issues with a minimal increase in process steps. A gate-last approach to realize a dual metal gate has not been discussed in this article, as the process complexity of this approach prohibits its practical implementation into manufacturing. Some noble metals, however, eventually may need a gate-last approach, due to difficulties in etching the material.
References
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S. C. Song is a project manager at Sematech, 2706 Montopolis Dr., Austin, TX 78741; ph 512/356-3544; e-mail [email protected].
M.M. Hussain is a project engineer at Sematech.
J. Barnett is a senior member of technical staff at Sematech.
B.S. Ju is a project engineer at Sematech.
B.H. Lee is a manager of the Advanced Gate Stack program at Sematech.