“Bulking up” with direct silicon bonding
07/01/2006
Layer-transfer technology is becoming more important as the demand for high-performance applications requiring enhanced semiconductor functions increases, and other applications such as MEMS and packaging continue to expand. A recently announced modification by Silicon Genesis Corp. (SiGen) of an existing layer-transfer process provides for direct silicon bonding (DSB) and electrically attaching a film of single-crystal silicon of differing crystal orientation onto a base substrate.
The resulting DSB substrate exhibits bulk-like properties, making it compatible with existing EDA and circuit design tools. “DSB is compatible with bulk Si because the SPICE models and libraries are developed for bulk and the wafer itself looks bulk-like,” explained Francois Henley, president & CEO of SiGen. “This is one of the big attractions for the foundries and the large microprocessor makers, [because] there is a significant advantage in not requiring an SOI substrate.”
Another advantage of DSB substrates is that they are compatible with the local process strain approaches used by many IC manufacturers. The bulk-like material also makes metrology easier, since SOI wafers have peculiar issues with respect to metrology. “But DSB looks, works, and feels like a bulk wafer,” said Henley. “For those in the manufacturing trenches, they would use essentially the same recipes in their tools and the same metrology and in-process measurements as they would in bulk.”
The main steps in SiGen’s DSB process are: 1) oxidizing and forming the cleave plane in the donor wafer, 2) bonding the donor and handle wafers, 3) room-temperature controlled cleaving (rT-CCP), 4) epi smoothing/thickening, a noncontact technology, and 5) a high-temperature proprietary anneal.
To arrive at its DSB process, SiGen modified the bonding and post-cleaving process steps. The revised process utilizes plasma-activated bonding, a hydrophilic bonding process that increases the surface energy (i.e., the amount of energy required to break the bond), making the bond stronger and resulting in fewer voids. While the benefit of plasma activation is a higher surface energy, the process results in a limited amount of a silicon-rich oxide layer that has to be eliminated. Eliminating this oxide layer is accomplished by doing the epi-smoothing process to make the surfaces pristine, followed by a high-temperature anneal that diffuses the oxygen out of the surface. Then the interfacial layers are subsequently regrown, or recrystallized, via solid-phase epitaxial regrowth (see figure).
One application for DSB is fabricating hybrid orientation substrates that combine the highest pMOS and nMOS mobilities. It is known that pMOS devices work better, i.e., hole mobility is highest, with a 110 surface orientation, resulting in a ~2× mobility improvement. Conversely, nMOS devices work better in a 100 orientation, i.e., electron mobility is highest. “You really can’t grow 110 on 100-nobody’s been able to do that, as far as I know,” said Henley. “What people want to do now is take a 100 wafer or a 110 wafer, and somehow put a thin film of the other crystal orientation on it. There’s really no other way to do it other than to layer-transfer a different crystal orientation on it.”
According to Henley, the generally accepted market size for SOI by 2009 is on the order of 10% of the whole semiconductor materials industry. He believes that DSB addresses more than 90% of the bulk market, as opposed to the much smaller SOI market. While the substrate cost is higher, Henley believes it can be offset by pMOS scaling and die shrinks for two scenarios. The first case is for low- to medium-performance devices in which there could be a higher die count/wafer with equivalent pMOS performance. The second case is for high-performance devices with an equivalent number of die/wafer, but with higher pMOS performance.
The modified DSB process is being sampled by device manufacturers, and Henley expects to report on results in the next few months. He anticipates that the bulk-like properties of DSB substrates and the resulting improvement in pMOS mobility will generate a substantially higher market demand than or SOI technology. -D.V.
AIN wafers commercially available, quality and price improving
The world’s largest aluminum nitride (AlN) single-crystal boules are now being grown and sliced into 2-in. wafers ready for epitaxial growth. Crystal IS Inc., Green Island, NY, has announced the limited availability of ~300µm thick wafers from AlN boules that are grown by sublimation and recondensation-not Czochralski or float-zone techniques-and then sliced and polished. “AlN is a very hard material, so polishing it is not as simple as you might think,” noted Timothy Bettles, VP of business development. X-ray topography measurements show that wafers average less than 1000 dislocations/cm2.
Crystal IS, co-founded in 1997 by Glen Slack and Leo Schowalter from RPI, got its start working under US government SBIR and DARPA grants, and only began looking at commercial applications of AlN in 2005. All intellectual property used by the company is owned by Crystal IS, for both crystal growth and polishing.
All other currently available AlN starting material is vapor-phase epitaxially (VPE) grown on top of silicon carbide, gallium arsenide, or sapphire substrates. The inherent lattice mismatch between any of these substrates and the AlN epi-layer results in dislocation densities in the range of single-digit 1000’s/cm2.
The <1000 dislocations/cm2 specification for Crystal IS’s AlN wafers is currently only held for ~50% of the 2-in. wafer surface; the company plans to be at 80% by year’s end, and targets 100% by the end of 2007. “We’re currently transitioning from R&D into manufacturing,” explained Bettles. For current customers, the material is said to already have fewer defects compared to hetero-epitaxial wafers, so customers should already see better functional die yield. Along with increasing the quality over the near term, the company also plans to simultaneously reduce wafer prices by increasing production volumes, improving yields, and further optimizing production flows.
Crystal IS thinks that its new 2-in. AlN wafers will enable broad commercial applications beyond the currently established market for high-power RF discretes. Highly electrically insulating and highly thermally conductive, the material is ideal for high-power applications such as cell phone base stations. Future markets include high-temperature electronic and optoelectronic devices, high-power microwave devices, UV optical detectors, and UV light-emitting diodes (UV-LED) and lasers.
An AlN UV-LED can reach 210nm wavelength, which efficiently kills many germs in water. In addition, bird flu and SARS can both be “controlled,” though not completely killed, by breaking down the DNA, as a manner of germicidal air-purification. With small size and low power consumption, UV-LEDs seem to be ideal as the heart of compact battery operated personal water purification units. Home under-counter water purification systems that use UV sources today must replace bulbs that can average $120/year. “We’re still waiting on the lifetime data for AlN UV-LEDs,” said Bettles, “but everyone knows that fewer dislocations equals longer lifetimes. It’s as simple as that.” -E.K.
Microwaves cook up batch RTP
Start-up company DSG Technologies uses microwave heating in its Axom-200/300 thermal processing batch tool for applications such as low-temperature curing, Cu annealing, low-temperature ozone oxidation, and low-temperature nitridation. While the use of microwaves for heating applications might conjure up images of last night’s dinner that didn’t get completely cooked in the microwave oven, Jeff Kowalski, president and CEO of DSG, dispels such comparisons with physics.
The key to the process is heating volumetrically, he explains. “Because silicon is so thin, one gets great depth of penetration-the entire wafer is heated uniformly-and there is superior temperature control.” Electromagnetic waves in the reactor accomplish the volumetric heating by oscillating molecules in the wafer. The company reports uniform wafer heating with temperature control to <1°C/wafer and, because the microwaves travel at the speed of light, energy transfer is fast (see figure). The frequency of the microwaves being used is 5.8GHz, more than twice that of home microwave ovens (~2.45GHz). The much higher frequency in combination with the thin silicon material enable the depth of penetration and uniform heating. “All the molecules across the wafer are heating at the same rate, so instead of heating from edge to center, you’re heating from the inside out,” Kowalski said.
 Ramp and stabilization curves for the Axom reactor vs. conventional furnaces. |
The use of higher-frequency microwaves, in combination with algorithms that control the power density, minimize power hotspots in the reactor. The proprietary technology is called micro-mode microwave, or M3. Additionally, the chamber design eliminates standing waves, the cause of uneven heating, or hotspots.
The speed-of-light travel also means heating is mass independent, so the wafer load size doesn’t matter. Kowalski points out that the tool can process both 200mm and 300mm wafer sizes in the same reactor, requiring only a change of the quartz rack that holds the wafers. The system is characterized as cold-walled because the microwave energy gets transmitted through the quartz wall and the wafers are positioned relatively far from it. Depending on the process, the wafers can be either under vacuum or atmospheric pressure.
While volumetric heating clearly distinguishes the reactor from other thermal processing technologies, another differentiator is that the system does not need thermocouples. Instead, IR sensors measure backside emissivity.
The company’s goal is not to replace traditional products, but rather to target 65nm-and-below processes that require very uniform thermal process characteristics. Kowalski views the combination of temperature control and the productivity of batch tools as key to reversing an industry trend seen with each process generation-namely, that vertical furnaces have lost market share to single-wafer tools.
“Through time and innovation, we can not only reclaim some of the processes that have gone to the single-wafer tools, but at the same time stop the migration of further processes going forward,” said Kowalski. The company’s production tool is currently in beta evaluation. -D.V.
Scientists apply “laser” focus to strip hydrogen from silicon
Researchers from the U. of Minnesota, Vanderbilt U., the U. of Tennessee, and Oak Ridge National Laboratory have developed a method to strip hydrogen atoms from silicon surfaces, a process that could enable production of silicon devices at nearly room temperature.
Silicon surfaces are exposed to hydrogen atoms in a “passivation” process to prevent oxidation during the semiconductor manufacturing process. The hydrogen atoms attach to all available silicon bonds, and must be removed before another silicon layer is applied. Desorbing the hydrogen thermally requires high temperatures, which can create thermal defects in the chips.
In previous work using lasers, molecules quickly absorbed and converted the light energy into heat, which indiscriminately broke the weakest bonds first, leaving targeted ones intact. In the new process, researchers used a free-electron laser operating in the infrared portion of the spectrum to tune the light to the frequency at which the hydrogen-silicon bonds vibrated and polarized, so that the photon’s electrical field was pointed in the same direction as the silicon-hydrogen bonds.
 Hydrogen desorption from silicon surfaces. |
“By selectively removing the hydrogen atoms from the ends of nanowires-structures typically 5-10nm wide-we should be able to control and direct their development, which currently is a random process,” stated U. of Minn. professor Philip Cohen. He indicated the technique could be used to manufacture field-effect transistors (FETs) that operate about 40% faster than ordinary transistors, while reducing processing temperatures by 100°C. It could also be used to extend a silicon crystal to make airtight seals around minuscule sensors.
“The fact that we have figured out how to remove hydrogen with a laser raises the possibility that we will be able to grow silicon devices at very low temperatures, close to room temperature,” added Vanderbilt prof. Norman Tolk.
Vanderbilt, the U. of Minnesota, and Oak Ridge National Labs are filing a joint patent on the process and its potential applications. Their work was described in the May 19 issue of the journal Science. -J.J.M.
Microgram scales provide resolution for nanometer-era process control
Dynamic sensing and compensation technology converts a precise mass-balance into an atomically precise one. With microgram resolution and repeatability in automated systems in the 10-milligram range, weight measurement tools from Metryx are currently installed on fab floors assisting in process development as well as routine statistical process control (SPC) tracking. Their newest Mentor DF3 tool includes dual 300mm FOUPs that can also handle 200mm wafers.
The systems use ambient sensors to continuously monitor temperature, pressure, and relative humidity. Sensing the air density allows weight measurement correction in the substrate’s atmospheric buoyancy. These dynamic software compensations and substantial hardware redesign and optimization to minimize internal noise sources allow for atomic-layer resolution without the extra size and cost of ambient isolation.
An atmospheric robot handles up to 60 wafers/hr in and out of the measurement enclosure. After the wafer reaches equilibrium with internal conditions, it is placed on a load-cell that determines weight. By taking “before and after” difference measurements, and comparing to reference and calibration masses, one can determine the change in mass due to a wide variety of both deposition and material-removal processes, with atomic-layer accuracy. The nondestructive technique can be used on 150mm to 300mm product, test, and blanket wafers.
Changes in material removal processes, such as wet-etch, plasma-etch, and chemical-mechanical planarization (CMP), can be detected and used in R&D. For example, a deep silicon etch on 200mm wafers with a 12% exposed area removes ~1µg for every 1µm of trench depth; for a target of 30µm, a 10% control range might be 3µm ≈ 3mg, and Metryx claims the systems’ 1σ mass error is 0.04mg, or just 0.7nm of silicon. This is ample bandwidth for R&D and also eventual manufacturing SPC.
Critical deposition films, including multicomponent or multiphase layers such as high-k and low-k materials, can be weighed to determine basic thickness as well as “2nd-order” information such as porosity of low-k and composition of high-k films. For HfSixOy atomic-layer deposition (ALD) films, the Si content must be controlled to ensure proper dielectric properties. With every hafnium atom having over 6× the atomic weight of every silicon atom, variations in content result in resolvable weight shifts (see figure). Changes of silicon of <1% can be simply, nondestructively detected during volume production.
 Silicon content vs. density for HfSixOy. |
The only downside to running wafers though the system is the backside addition of particles due to the necessarily intimate contact between the wafer and the balance. However, it would seem that measurements could be done just before cleans in an existing manufacturing flow without any concern. -E.K.