The Open Modeling Coalition creates a new effective current source model
07/01/2006
New models are needed to account for the process variations in nanometer-era silicon manufacturing, so that new chips can be designed with acceptable yield and performance without requiring costly re-spins. The Silicon Integration Initiative’s Open Modeling Coalition (OMC) has released an effective current source model (ECSM) that provides inputs to a static design library, while dynamic extensions are currently under development. The ECSM allows for accurate timing analysis and can show the locations of yield-limiting “hot spots” that can be eliminated in a design. Future models will also deal with power analysis and signal integrity.
Advances in semiconductor technology have dramatically fueled growth in the consumer, telecommunication, and computing sectors. Each new technology node brings greater functionality, lower product cost, and increased battery life, permitting new products to come to market that were not previously feasible. However, as device sizes continue to shrink, the need to accurately represent the hitherto unaccounted for “physical” effects continues to grow, as complications increase in both design tools and methodologies.
Circuit elements now require more accurate modeling to support a number of issues, including lower-power designs that employ multiple voltage levels, the long interconnects and meshes seen in buses and clock networks, and the influence of voltage on delay as seen in IR-drop analysis and dynamic voltage scaling. The goal of these new models is to enable design engineers to identify and correct problems pre-tape-out, which would otherwise be observed only later in silicon by the manufacturing engineers.
Silicon Integration Initiative’s (Si2) Design Technology Council together with major EDA vendors identified the need to establish a collaborative effort to introduce new modeling technologies. In 2005, Si2 launched the Open Modeling Coalition (OMC) to address the modeling issues that were being seen at 90nm and beyond. The coalition approaches the problem in a comprehensive manner, from device characterization to model generation, and from model access to actual use by design tools. A two-prong approach is being pursued using both dynamic executable models for increased flexibility in the future as well as the more traditional static library descriptions for compatibility with today’s existing design environments.
Static models
Earlier this year, Si2 announced the first result of this collaboration, the ECSM 2.0 specification. The ECSM specification is a static library description that is compatible with the Synopsys Liberty syntax. Within the OMC, the ECSM change management group (CMG), which produced the specification, has representatives from industry leaders Cadence Design Systems, Freescale Semiconductor, Intel, LSI Logic, Magma Design Automation, Silicon Navigator, Sun Microsystems, and Virage Logic. This group is now actively working to extend ECSM to support the analysis of power, signal integrity, and the effects of manufacturing process variations on timing and power.
 Figure 1. ECSM model for driver and receiver. (Courtesy: Cadence Design Systems) |
ECSM allows additional modeling information to be passed from a characterization system to design tools that enable more accurate delay prediction. ECSM uses a current-source driver model as shown in Fig. 1, to model the cell’s nonlinear output behavior. This model predicts actual silicon performance more accurately than today’s traditional single lumped effective-capacitance wire-load models. Although the circuit is modeled as a current source, ECSM allows the library creator to simplify the characterization process by measuring the output waveform as a series of voltage-vs.-time curves. These curves are then converted into current values internally by the analysis tool.
 Figure 2. ECSM driver model example. (Courtesy: Cadence Design Systems) |
ECSM libraries do not represent propagation delays and slews explicitly. Rather, delays are computed based on the input signal slopes and the output load of the circuit. The driver waveforms are represented as a series of voltage-vs.-time measurements for the various loads on the circuit, as shown in Fig. 2. Each may be sampled at different combinations of slew and load values so that waveforms that are predominantly linear can be represented with fewer sample points.
Dynamic models
Accurate modeling of power in designs at ≤90nm requires the adoption of dynamic power analysis rather than the more traditional static approach. The OMC is extending ECSM to allow power and dynamic power-grid analysis information to be passed to the design tools, enabling them to perform accurate dynamic IR-drop analysis. The extensions include modeling the dynamic current signatures of power and ground pins as a current waveform vs. time and modeling the resistances and effective capacitances of power rails for cells in the design library. This new information allows design tools to perform effective dynamic power grid analysis and to identify potential problem areas in the design.
Using the information provided by ECSM, it is possible to calculate actual current drawn from the power grid at any given time for individual cells. This approach allows a power map to be created for the chip showing the actual power used in the various areas as a function of time. Potential hot spots that may degrade yield and performance can be identified early in the design process when they are more easily fixed. Through this anticipatory process of checking and correcting problems before committing a design to silicon, it is possible to reduce the number of design-turns in manufacturing, as well as the associated costs, and to accelerate the time-to-market for the product.
Signal integrity (SI) analysis, specifically for noise, has been critical since the 180nm technology node. Long thin wires exist in closer proximity to each other and introduce significant electrical coupling between unrelated circuit elements, which can create spurious signals (noise) on “victim” nets as well as adversely affect circuit timing. The effect of this crosstalk and induced noise can be lower performance, incorrect circuit functionality, and decreased circuit reliability. Existing approaches to SI tend to be based on vendor-developed proprietary formats.
The OMC recognized the importance of supporting the creation of SI modeling information in the characterization flow, and assigned CMG the task of defining the necessary extensions to ECSM to support the capture and transfer of SI models. Library elements will by extended by modeling the effect of a coupled signal transition on a driver that is not currently switching states. In addition, glitches within the circuit may be propagated through the library elements; however, accurate modeling of this effect often requires SPICE-level simulation within the analysis tools as part of the overall design closure flow.
ECSM is also being extended to deal with parametric variability resulting from manufacturing-process variability in steps such as lithography and CMP. This, in turn, requires variability analyses of timing and power by the designer. Traditional guard-banding approaches that account for the effects of process variations necessarily result in pessimistic timing. With characterizations of these process variations and statistical timing analysis techniques, product designers will be able to use the performance improvement of advanced technology nodes while maintaining controlled and acceptable wafer yields.
Future directions
Similar techniques can be applied for both power and SI analysis. The OMC has formed a statistical working group (SWG) to standardize the necessary statistical modeling information that IP developers must provide to enable these analyses. The SWG is currently focused on transistor-based process variations, on correlated and uncorrelated distributions for both global variations (die-to-die) as well as local variations (mismatch within 100µm). The roadmap for this working group has targeted a specification for statistical power modeling by the end of this year.
Continued advances in semiconductor technology require sophisticated modeling technologies to account for ever greater instances of inter-related physical phenomena. New models are needed for the parasitic effects of self and mutual inductance, and for the treatment of interdependent effects of power, timing, noise, and many other factors. The dis-aggregation of the electronics design chain requires companies to collaborate to produce new modeling technologies. Si2, through the formation of the OMC, is addressing this demand. The first deliverable of this collaboration, the ECSM 2.0 specification, has already been released and is available from the Si2 website at http://openeda.si2.org/projects/omcdistrib/.
Acknowledgments
Synopsys is a registered trademark and Liberty is a trademark of Synopsys Inc.
Bob Carver is director of business development at Silicon Integration Initiative Inc., 9111 Jollyville Rd, Suite 250, Austin, TX 78759; ph 512/342-2244, e-mail [email protected].